A 256-kb 65-nm Sub-threshold SRAM Design for Ultra-Low-Voltage Operation

[seminar surveyer]

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Benton Highsmith Calhoun, Member, IEEE, and Anantha P. Chandrakasan, Fellow, IEEE

Abstract—
Low-voltage operation for memories is attractive because of lower leakage power and active energy, but the challenges of SRAM design tend to increase at lower voltage. This paper explores the limits of low-voltage operation for traditional six–transistor (6 T) SRAM and proposes an alternative bitcell that functions to much lower voltages. Measurements confirm that a 256-kb 65-nm SRAM test chip using the proposed bitcell operates into sub-threshold to below 400 mV. At this low voltage, the memory offers substantial power and energy savings at the cost of speed, making it well-suited to energy-constrained applications. The paper provides measured data and analysis on the limiting effects for voltage scaling for the test chip.


for more:
http://docs.googleviewer?a=v&q=cache:KiX...fGzdnvXImg

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