24-12-2010, 12:54 PM
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INTRODUCTION
Recent growth in high-end processors, multi-media, virtual reality and networking has demanded more bandwidth than ever before. But the point-to-point physical layer interfaces have not been able to deal with moving information at the data rates required. Some of today’s biggest challenges that remain to be solved include: the ability to transfer data fast, lower power systems than currently available, and economical solutions to overcome the physical layer bottleneck.
Data Transmission standards like RS-422, RS-485, SCSI and others all have their own limitations most notably in transferring raw data across a media. Not anymore. Low Voltage Differential Signaling (LVDS) is a high speed (>155.5 Mbps), low power general purpose interface standard that solves the bottleneck problems while servicing a wide range of application areas.
This application note explains the key advantages and benefits of LVDS technology. Throughout this application note the DS90C031 (LVDS 5V Quad CMOS Differential Line Driver) and the DS90C032 (LVDS 5V Quad CMOS Differential Line Receiver) will be used to illustrate the key points. Over 50 LVDS devices are offered currently (1998) from National, please refer to the LVDS device datasheets for complete specifications.
Low-voltage differential signaling, or LVDS, is an electrical signaling system that can run at very high speeds over inexpensive twisted-pair copper cables. It was introduced in 1994, and has since become very popular in computers, where it forms part of very high-speed networks and computer buses.
Low-voltage differential signaling (LVDS) is a signaling method used for high-speed transmission of binary data over copper. It is well recognized that the benefits of balanced data transmission begin to outweigh the costs over single-ended techniques when signal transition times approach 10 ns. This represents signaling rates of about 30Mbps or clock rates of 60MHz (in single-edge clocking systems) and above. LVDS, as documented in TIA/EIA-644, can have signal transition time as short as 260ps turning a printed circuit board trace into a transmission line in a few centimeters. Care must be taken when designing with LVDS circuits, such as the SN65LVDS31 quadruple line driver and SN65LVDS32 quadruple line receiver. This document provides some guidelines for the basic application of LVDS.
What is Differential Signaling?
Differential signaling is a method of transmitting information electrically by means of two complementary signals sent on two separate wires. The technique can be used for both analog signaling, as in some audio systems, and digital signaling, as in RS-422, RS-485, Ethernet (twisted-pair only), PCI Express and USB. The opposite technique, which is more common but lacks some of the benefits of differential signaling, is called single-ended signaling.
There are plenty of choices when selecting a high-speed differential signaling technology. Differential technologies generally share certain characteristics but vary widely in performance, power consumption, and target applications. Table 1-1 lists various attributes of the most common differential signaling technologies.
Industry standards bodies define LVDS and M-LVDS technologies in specifications ANSI/TIA/EIA-644A and ANSI/TIA/EIA-899, respectively. Some vendor datasheets claim LVDS I/Os (or pseudo-LVDS) but in fact may not meet the required common mode or some other important parameter. Therefore, compliance to the LVDS specification TIA/EIA-644A is an important consideration.Current-Mode Logic (CML) and Low-Voltage Positive-Emitter-Coupled Logic (LVPECL) are widely used terms throughout the industry, although neither technology conforms to any standard controlled by an official standards organization. Implementations and device specifications will therefore often vary between vendors. AC coupling is used extensively which helps resolve threshold differences that might otherwise cause compatibility issues. Note that all of the technologies listed are differential and thus share the advantages common to differential signaling such as excellent noise immunity and low device-generated switching noise.
A typical LVDS driver – receiver pair is shown in Figure 1. A (nominal) 3.5mA current source is located in the driver. Since the input impedance of the receiver is high, the entire current effectively flows through the 100Ω termination resulting in a (nominal) 350 mV voltage across the receiver inputs. The receiver threshold is guaranteed to be 100 mV or less, and this sensitivity is maintained over a wide common mode from 0V to 2.4V. This combination provides excellent noise margins and tolerance to common-mode shifts between the driver and receiver. Changing the current direction results in the same amplitude but opposite polarity at the receiver. Logic ones and zeros are generated in this manner. CML and LVPECL have a similar architecture but with different strength current sources and termination schemes.
INTRODUCTION
Recent growth in high-end processors, multi-media, virtual reality and networking has demanded more bandwidth than ever before. But the point-to-point physical layer interfaces have not been able to deal with moving information at the data rates required. Some of today’s biggest challenges that remain to be solved include: the ability to transfer data fast, lower power systems than currently available, and economical solutions to overcome the physical layer bottleneck.
Data Transmission standards like RS-422, RS-485, SCSI and others all have their own limitations most notably in transferring raw data across a media. Not anymore. Low Voltage Differential Signaling (LVDS) is a high speed (>155.5 Mbps), low power general purpose interface standard that solves the bottleneck problems while servicing a wide range of application areas.
This application note explains the key advantages and benefits of LVDS technology. Throughout this application note the DS90C031 (LVDS 5V Quad CMOS Differential Line Driver) and the DS90C032 (LVDS 5V Quad CMOS Differential Line Receiver) will be used to illustrate the key points. Over 50 LVDS devices are offered currently (1998) from National, please refer to the LVDS device datasheets for complete specifications.
Low-voltage differential signaling, or LVDS, is an electrical signaling system that can run at very high speeds over inexpensive twisted-pair copper cables. It was introduced in 1994, and has since become very popular in computers, where it forms part of very high-speed networks and computer buses.
Low-voltage differential signaling (LVDS) is a signaling method used for high-speed transmission of binary data over copper. It is well recognized that the benefits of balanced data transmission begin to outweigh the costs over single-ended techniques when signal transition times approach 10 ns. This represents signaling rates of about 30Mbps or clock rates of 60MHz (in single-edge clocking systems) and above. LVDS, as documented in TIA/EIA-644, can have signal transition time as short as 260ps turning a printed circuit board trace into a transmission line in a few centimeters. Care must be taken when designing with LVDS circuits, such as the SN65LVDS31 quadruple line driver and SN65LVDS32 quadruple line receiver. This document provides some guidelines for the basic application of LVDS.
What is Differential Signaling?
Differential signaling is a method of transmitting information electrically by means of two complementary signals sent on two separate wires. The technique can be used for both analog signaling, as in some audio systems, and digital signaling, as in RS-422, RS-485, Ethernet (twisted-pair only), PCI Express and USB. The opposite technique, which is more common but lacks some of the benefits of differential signaling, is called single-ended signaling.
There are plenty of choices when selecting a high-speed differential signaling technology. Differential technologies generally share certain characteristics but vary widely in performance, power consumption, and target applications. Table 1-1 lists various attributes of the most common differential signaling technologies.
Industry standards bodies define LVDS and M-LVDS technologies in specifications ANSI/TIA/EIA-644A and ANSI/TIA/EIA-899, respectively. Some vendor datasheets claim LVDS I/Os (or pseudo-LVDS) but in fact may not meet the required common mode or some other important parameter. Therefore, compliance to the LVDS specification TIA/EIA-644A is an important consideration.Current-Mode Logic (CML) and Low-Voltage Positive-Emitter-Coupled Logic (LVPECL) are widely used terms throughout the industry, although neither technology conforms to any standard controlled by an official standards organization. Implementations and device specifications will therefore often vary between vendors. AC coupling is used extensively which helps resolve threshold differences that might otherwise cause compatibility issues. Note that all of the technologies listed are differential and thus share the advantages common to differential signaling such as excellent noise immunity and low device-generated switching noise.
A typical LVDS driver – receiver pair is shown in Figure 1. A (nominal) 3.5mA current source is located in the driver. Since the input impedance of the receiver is high, the entire current effectively flows through the 100Ω termination resulting in a (nominal) 350 mV voltage across the receiver inputs. The receiver threshold is guaranteed to be 100 mV or less, and this sensitivity is maintained over a wide common mode from 0V to 2.4V. This combination provides excellent noise margins and tolerance to common-mode shifts between the driver and receiver. Changing the current direction results in the same amplitude but opposite polarity at the receiver. Logic ones and zeros are generated in this manner. CML and LVPECL have a similar architecture but with different strength current sources and termination schemes.
