Integrated Implantable Stimulator without Off-Chip Blocking-Capacitors

[science projects buddy]

Fail Safe Implantable Stimulator without off chip capacitors
Denny Mathew
S7 AEI
College Of Engineering,Trivandrum
2007-11 Batch

INDEX
Introduction to Neural Stimulator
FES systems
Blocking Capacitors
HFCS Technique
Current Generator Circuit
Architecture
Conclusion


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INTRODUCTION
Neural Stimulators delivers electrical stimulations to restore limb motion
Functional Electrical Stimulation (FES) stimulates nerves and muscles
Applies a train of current pulses eliciting muscle response
Placed in
FES System
Benefited from packaging technology advancements
referred to as Neuromuscular electrical stimulation (NMES)
Stimulation pulses include cathodic and anodic phase with inter phase delay
Uses blocking Capacitors for adequate safety placed off chip

Stimulator With Off chip capacitors
Blocking Capacitors
Prevents serious injury under faulty conditions
Placed in series with each electrode
ensures charge density to chosen safe limit
Qmax=C x V
Maintains Charge balance


Associated Problems
Large capacitance value hinders integration
Large physical size of the unit increasing power needs
Serious Limitation in developing multi- channel stimulators
Alternative Methods
Using polarizable electrode such as iridium oxide Or porous platinum
Monitoring of stimulus current level voltage or electrode impedance
A precise bi phasic stimulation
Through Novel cicuits
HFCS ckts-High Frequency Circuit Switching
Current Generator ckts

HFCS Technique
C=Istim X T / V
Shorter charging periods leads to smaller C values
Stimulus current made summation of High frequency pulses
Renders device fail safe while reducing the capacitance levels


Timing Waveform
O/p Stage
Novel Current Generator Circuit
Contd..
All current sink transistors exhibit same mobility degradation
Drain Current of each transistor


Output current
. ID
Reduced complexity silicon area and power
Linearity unaffected by Mobility degradation

Stimulator Architecture

Consists essentially of
4 bit current generator DAC
Two voltage controlled oscillators
High voltage charge pump
Digital control logic
Electrode driving circuit
VCO2 provide switching frequency: 5-50Mhz



Advantages
Miniaturization while being fail safe
High density neural stimulation interface
Decrease in overall power consumption
200uW for 1 ma 20 hz in-vitro tests
Will restore more functions for patients

References
J.-J. Sit and R. Sarpeshkar, “A low-power blocking-capacitor-freecharge-balanced electrode-stimulator chip with less than 6 nA DCerror for 1-mA full-scale stimulation,” IEEE Trans. Biomed. CircuitsSyst., vol. 1, no. 3, pp. 172–183, Sep. 2008.
Xiao Liu, Andreas Demosthenous and Nick Donaldson “An Integrated Implantable Stimulator That is Fail-Safe Without Off-Chip Blocking-Capacitors”.IEEE Trans. Biomed. CircuitsSyst., vol. 2, no. 3, pp. 172–183, Sep. 2009
X. Liu, A. Demosthenous, and N. Donaldson, “A fully integrated failsafe stimulator output stage dedicated to FES stimulation,” in Proc.2007 IEEE Int. Symp. Circuits Syst. (ISCAS’07), New Orleans, LA,May 2008, pp. 2076–2079.
J.-J. Sit and R. Sarpeshkar, “A low-power blocking-capacitor-free charge-balanced electrode-stimulator chip with less than 6 nA DC error for 1-mA full-scale stimulation,” IEEE Trans. Biomed. Circuits Syst., vol. 1, no. 3, pp. 172–183, Sep. 2007.