19-06-2010, 07:39 PM
Abstract
A novel reconfigurable low-power high-performance matrix multiplier architecture and its component circuits are described in this article. The processor can be simply reconfigured to calculate the product of matrices X[n,K] and Y[k,m] where n, k, m are integers and b being the precision which ranges from 4 to 64 bits and maximizing the utilization of the hardware available. To illustrate this , the hardware equivalent to one 64×64 bit high precision multiplier can be reconfigured to produce the product of two matrices X8×8 and Y8×8 of 8-bit items in 9 pipeline cycles. The matrix multiplier of size s may consist of an array of (s/m)^2 of m×m. may consist of an array of (s/m)2 of m×m small multipliers utilized in the design.
A Reconfigurable Low-power High-Performance Matrix Multiplier Architecture With Borrow Parallel Counters Counters
The Partial Product Decomposition-Based Arithmetic Architecture:Here the The 4x4 partial product matrix, the addition of the partial product bits, multiplication of two 8-bit numbers using four 4x4 multipliers etc have been shown.Utilizing partial product bit matrix decomposition for full self-testability, Utilizing borrow bits for simple circuit and high speed, more importantly, reducing pass-transistor path length (no more than 4) and rearranging and balancing input bits to each column of small multipliers are done. For more info refer these:
[attachment=3805]
A novel reconfigurable low-power high-performance matrix multiplier architecture and its component circuits are described in this article. The processor can be simply reconfigured to calculate the product of matrices X[n,K] and Y[k,m] where n, k, m are integers and b being the precision which ranges from 4 to 64 bits and maximizing the utilization of the hardware available. To illustrate this , the hardware equivalent to one 64×64 bit high precision multiplier can be reconfigured to produce the product of two matrices X8×8 and Y8×8 of 8-bit items in 9 pipeline cycles. The matrix multiplier of size s may consist of an array of (s/m)^2 of m×m. may consist of an array of (s/m)2 of m×m small multipliers utilized in the design.
A Reconfigurable Low-power High-Performance Matrix Multiplier Architecture With Borrow Parallel Counters Counters
The Partial Product Decomposition-Based Arithmetic Architecture:Here the The 4x4 partial product matrix, the addition of the partial product bits, multiplication of two 8-bit numbers using four 4x4 multipliers etc have been shown.Utilizing partial product bit matrix decomposition for full self-testability, Utilizing borrow bits for simple circuit and high speed, more importantly, reducing pass-transistor path length (no more than 4) and rearranging and balancing input bits to each column of small multipliers are done. For more info refer these:
[attachment=3805]
