22-03-2010, 07:08 PM
[attachment=2747]
An Overview of Serial ATA Technology
Objectives
Why SATA was invented
The differences between PATA and SATA
How the hardware is structured to transmit and receive SATA
Protocol of SATA transmission
What is PATA
All of the below synonyms refer to a modern day PATA drive
PATA “ Parallel Advanced Technology Attachment
UDMA “ Ultra Direct Memory Access
IDE “ Integrated Device Electronics
EIDE “ Enhanced IDE
More on PATA
40 & 80 wire cable option
40 wire limited to UDMA 33 MB/s and below
80 wire allowed for UDMA 66, 100, 133 MB/s
Required by ATA spec to be 5v tolerant (3.3v has been the norm for several years)
Must support Master/Slave/Cable Select
SATA Basics
New Connector
Saves space
More reliable
More air flow
Connector has 4 transmission wires
Tx differential pair
Rx differential pair
SATA Basics
SATA I for 1.5Gbps ~ 150MB/s
SATA II for 3.0Gbps ~ 300MB/s
Provides support for legacy command set
Includes new commands for SATA BIST and power management
Connectivity
Serial ATA is point-to-point topology
Hosts can support multiple devices but requires multiple links
100% available page link bandwidth
Failure of one device or page link does not affect other links
Link Characteristics
SATA uses full-duplex links
Protocol only permits frame transfer in one direction at a time
Each page link consists of a transmit and a receive pair
SATA uses low voltage levels
Nominal voltage +/-250mV differential
Power Management
SATA has
Phy Ready “ Capable of sending and receiving data. Main phase locked loop are on and active
Partial “ Physical layer is powered but in a reduced state. Must be able to return to Phy Ready within 10 us.
Slumber “ Physical layer is powered but in a reduced state. Must be able to return to Phy Ready within 10 ms.
ATA also defines IDLE, STANDBY, and SLEEP
Necessary for newer laptop & mobile devices
SATA Architectural Model
Physical Layer
Transmission (Tx) and Reception (Rx) of a 1.5Gb/s serial stream
Perform power on sequencing
Perform speed negotiation
Provide status to page link layer
Support power management requests
Out-of-Band (OOB) signal generation and detection
Out of Band
Part of normal power on sequence
Allows host to issue a device hard reset
Allows device to request a hard reset
Brings device out of low power state
Out of Band Signals
COMRESET
Always originated by the host
Forces a hard reset in the device
Used to start page link initialization
COMINIT
Always originated by the device
Requests a page link reset
Issued by device in response to COMRESET
Out of Band Signals (cont.)
COMWAKE
Can be originated by either host or device
Used as final phase of OOB initialization
Used to bring out of low power & test states
Exit Partial
Exit Slumber
Exit BIST
Out of Band Signal Forms
Out of Band Signaling Protocol
SATA Port Model
SATA Architectural Model
Link Layer
8b / 10b encoding
Scrambles and descrambles data and control words
Converts data from transport layer into frames
Conduct CRC generation and checking
Provides frame flow control
Encoding Concepts
All 32 bit Dwords are encoded for SATA
32 bits data = 40 bits of transmission
Provides sufficient transition density
Guarantees transition (0s and 1s) even if data is 0x00 or 0xFF
Provides an easy way to detect transmission error
Current Running Disparity (CRD)
As each character is encoded a count is maintained of the number of 0â„¢s and 1â„¢s being transmitted
More 1â„¢s than 0â„¢s give positive disparity
More 0â„¢s than 1â„¢s gives negative disparity
Same number gives neutral disparity
Only valid values of CRD are -1 and 1
Any other value indicates that a transmission error has occurred
CRD+ & CRD- Encoded Characters
SATA Primitives
Convey real-time state information
Control transfer of information between host and device
Provide host/device coordination
SATA Primitives
ALIGN “ Speed negotiation and at least every 256 Dword
SYNC “ Used when in idle to maintain bit synchronization
CONT “ Used to suppress repeated primitives
SATA Primitives
X_RDY
R_RDY
R_IP
R_OK
R_ERR
SATA Frame Structure
All SATA frames consist of:
A start of frame (SOF) delimiter
A payload “ transport layer information
A Cyclic Redundancy Check (CRC)
An end of frame (EOF) delimiter
Link Layer Protocol (1)
Link Layer Protocol (2)
Link Layer Protocol (3)
Link Layer Protocol (4)
Link Layer Protocol (5)
Link Layer Protocol (6)
Link Layer Protocol (7)
Link Layer Protocol (8)
Link Layer Protocol (9)
Link Layer Protocol (last)
SATA Architectural Model
Transport Layer
Responsible for the management of Frame Information Structures (FIS)
At the command of Application layer:
Format the FIS
Make frame transmission request to Link layer
Pass FIS contents to Link layer
Receive transmission status from Link layer and reports to Application layer
Frame Information Structure (FIS)
A FIS is a mechanism to transfer information between host and device application layers
Shadow Register Block contents
ATA commands
Data movement setup information
Read and write data
Self test activation
Unique FIS Type Code
FIS types
Register “ Host to Device FIS
BIST Activate FIS
Data FIS
SATA Architectural Model
Command / Application Layer
Defined using a series of state diagrams
Register H D
Register D H
DMA data in
DMA data out
Host command layer may be the same but may only support legacy commands
Completed !!
Any Question Comments
An Overview of Serial ATA Technology
Objectives
Why SATA was invented
The differences between PATA and SATA
How the hardware is structured to transmit and receive SATA
Protocol of SATA transmission
What is PATA
All of the below synonyms refer to a modern day PATA drive
PATA “ Parallel Advanced Technology Attachment
UDMA “ Ultra Direct Memory Access
IDE “ Integrated Device Electronics
EIDE “ Enhanced IDE
More on PATA
40 & 80 wire cable option
40 wire limited to UDMA 33 MB/s and below
80 wire allowed for UDMA 66, 100, 133 MB/s
Required by ATA spec to be 5v tolerant (3.3v has been the norm for several years)
Must support Master/Slave/Cable Select
SATA Basics
New Connector
Saves space
More reliable
More air flow
Connector has 4 transmission wires
Tx differential pair
Rx differential pair
SATA Basics
SATA I for 1.5Gbps ~ 150MB/s
SATA II for 3.0Gbps ~ 300MB/s
Provides support for legacy command set
Includes new commands for SATA BIST and power management
Connectivity
Serial ATA is point-to-point topology
Hosts can support multiple devices but requires multiple links
100% available page link bandwidth
Failure of one device or page link does not affect other links
Link Characteristics
SATA uses full-duplex links
Protocol only permits frame transfer in one direction at a time
Each page link consists of a transmit and a receive pair
SATA uses low voltage levels
Nominal voltage +/-250mV differential
Power Management
SATA has
Phy Ready “ Capable of sending and receiving data. Main phase locked loop are on and active
Partial “ Physical layer is powered but in a reduced state. Must be able to return to Phy Ready within 10 us.
Slumber “ Physical layer is powered but in a reduced state. Must be able to return to Phy Ready within 10 ms.
ATA also defines IDLE, STANDBY, and SLEEP
Necessary for newer laptop & mobile devices
SATA Architectural Model
Physical Layer
Transmission (Tx) and Reception (Rx) of a 1.5Gb/s serial stream
Perform power on sequencing
Perform speed negotiation
Provide status to page link layer
Support power management requests
Out-of-Band (OOB) signal generation and detection
Out of Band
Part of normal power on sequence
Allows host to issue a device hard reset
Allows device to request a hard reset
Brings device out of low power state
Out of Band Signals
COMRESET
Always originated by the host
Forces a hard reset in the device
Used to start page link initialization
COMINIT
Always originated by the device
Requests a page link reset
Issued by device in response to COMRESET
Out of Band Signals (cont.)
COMWAKE
Can be originated by either host or device
Used as final phase of OOB initialization
Used to bring out of low power & test states
Exit Partial
Exit Slumber
Exit BIST
Out of Band Signal Forms
Out of Band Signaling Protocol
SATA Port Model
SATA Architectural Model
Link Layer
8b / 10b encoding
Scrambles and descrambles data and control words
Converts data from transport layer into frames
Conduct CRC generation and checking
Provides frame flow control
Encoding Concepts
All 32 bit Dwords are encoded for SATA
32 bits data = 40 bits of transmission
Provides sufficient transition density
Guarantees transition (0s and 1s) even if data is 0x00 or 0xFF
Provides an easy way to detect transmission error
Current Running Disparity (CRD)
As each character is encoded a count is maintained of the number of 0â„¢s and 1â„¢s being transmitted
More 1â„¢s than 0â„¢s give positive disparity
More 0â„¢s than 1â„¢s gives negative disparity
Same number gives neutral disparity
Only valid values of CRD are -1 and 1
Any other value indicates that a transmission error has occurred
CRD+ & CRD- Encoded Characters
SATA Primitives
Convey real-time state information
Control transfer of information between host and device
Provide host/device coordination
SATA Primitives
ALIGN “ Speed negotiation and at least every 256 Dword
SYNC “ Used when in idle to maintain bit synchronization
CONT “ Used to suppress repeated primitives
SATA Primitives
X_RDY
R_RDY
R_IP
R_OK
R_ERR
SATA Frame Structure
All SATA frames consist of:
A start of frame (SOF) delimiter
A payload “ transport layer information
A Cyclic Redundancy Check (CRC)
An end of frame (EOF) delimiter
Link Layer Protocol (1)
Link Layer Protocol (2)
Link Layer Protocol (3)
Link Layer Protocol (4)
Link Layer Protocol (5)
Link Layer Protocol (6)
Link Layer Protocol (7)
Link Layer Protocol (8)
Link Layer Protocol (9)
Link Layer Protocol (last)
SATA Architectural Model
Transport Layer
Responsible for the management of Frame Information Structures (FIS)
At the command of Application layer:
Format the FIS
Make frame transmission request to Link layer
Pass FIS contents to Link layer
Receive transmission status from Link layer and reports to Application layer
Frame Information Structure (FIS)
A FIS is a mechanism to transfer information between host and device application layers
Shadow Register Block contents
ATA commands
Data movement setup information
Read and write data
Self test activation
Unique FIS Type Code
FIS types
Register “ Host to Device FIS
BIST Activate FIS
Data FIS
SATA Architectural Model
Command / Application Layer
Defined using a series of state diagrams
Register H D
Register D H
DMA data in
DMA data out
Host command layer may be the same but may only support legacy commands
Completed !!
Any Question Comments
