VHDL (VHSIC Hardware Description Language)
#1

[attachment=12000]
INTRODUCTION
VHDL (VHSIC Hardware Description Language) is a language for describing hardware. Its requirement emerged during the VHSIC development program of the US Department of Defense. The department organized a work shop in 1981 to lay down the specifications of a language which could describe hardware at various levels of abstractions, could generate test signals and record responses, and could act as a medium of information exchange between the chip foundries and the CAD tool operators. However, due to military restrictions, it remained classified till 1985.
There was a large participation of the private sector electronics industry in the development of the language. It felt that there was a need to make the language industry standard. In 1985, the DOD granted a permission to hand over the specs to IEEE. Subsequently IEEE released the
IEEE 1076/A standard in 1987. It was later revised in 1993. The 1993 revisions are minor and many of the simulation and synthesis tools have not yet adopted them. It is an object-oriented language and therefore people familiar with C++ or PASCAL can grasp it easily.
VHDL can wear many hats. It is being used for documentation, verification, and synthesis of large digital designs. This is actually one of the key features of VHDL, since the same VHDL code can theoretically achieve all three of these goals, thus saving a lot of effort. In addition to being used for each of these purposes, VHDL can be used to take three different approaches to describing hardware. These three different approaches are the structural, data flow, and behavioral methods of hardware description. Most of the time a mixture of the three methods is employed. The following sections introduce you to the language by examining its use for each of these three methodologies.
Structural Descriptions
We will discuss the first of the three approaches to design with VHDL, the structural description.
Building Blocks
To make designs more understandable and maintainable, a design is typically decomposed into several blocks. These blocks are then connected together to form a complete design. Using the schematic capture approach to design, this might be done with a block diagram editor. Every portion of a VHDL design is considered a block. A VHDL design may be completely described in a single block, or it may be decomposed in several blocks. Each block in VHDL is analogous to an off-the-shelf part and is called an entity. The entity describes the interface to that block and a separate part associated with the entity describes how that block operates. The interface description is like a pin description in a data book, specifying the inputs and outputs to the block. The description of the operation of the part is like a schematic for the block.
The following is an example of an entity declaration in VHDL.
entity latch is
port (s,r: in bit;
q,nq: out bit);
end latch;
The first line indicates a definition of a new entity, whose name is latch. The last line marks the end of the definition. The lines in between, called the port clause, describe the interface to the design. The port clause contains a list of interface declarations. Each interface declaration defines one or more signals that are inputs or outputs to the design.
Each interface declaration contains a list of names, a mode, and a type. In the first interface declaration of the example, two input signals are defined, s and r. The list to the left of the colon contains the names of the signals, and to the right of the colon is the mode and type of the signals. The mode specifies whether this is an input (in), output (out), or both (inout). The type specifies what kind of values the signal can have. The signals s and r are of mode in (inputs) and type bit. Next the signals q and nq are defined to be of the mode out (outputs) and of the type bit (binary).
All of the signals in the example are defined to be of the type bit. The type bit is a predefined type that can have two values represented by '0' and '1'. This type is used to represent two level logic signals.
The second part of the description of the latch design is a description of how the design operates. This is defined by the architecture declaration. The following is an example of an architecture declaration for the latch entity.
architecture dataflow of latch is
signal q0: bit: = '0';
signal nq0: bit: = '1';
begin
q0<=r nor nq0;
nq0<=s nor q0;
nq<=nq0;
q<=q0;
end dataflow;
The first line of the declaration indicates that this is the definition of a new architecture called dataflow and it belongs to the entity named latch. So this architecture describes the operation of the latch entity. The lines in between the begin and end describe the latch's operation. This example uses the data flow approach which is discussed later, so we won't discuss the meaning of these lines here. The next section explains how to specify the latch's operation using the structural approach.
Connecting Blocks
Once we have defined the basic building blocks of our design using entities and their associated architectures, we can combine them together to form other designs. This section describes how to combine these blocks together in a structural description.
Let's specify the operation of the latch entity used in the previous section by connecting some previously defined entities. The entity declaration for the latch was:
Reply

Important Note..!

If you are not satisfied with above reply ,..Please

ASK HERE

So that we will collect data for you and will made reply to the request....OR try below "QUICK REPLY" box to add a reply to this page
Popular Searches: vhdl hardware description languages, electronic device description language, seminar topics of hardware description language, hardware description language definition, hardware description language vhdl viva questions and answers, hardware description language, hardware description language for booths algorithm,

[-]
Quick Reply
Message
Type your reply to this message here.

Image Verification
Please enter the text contained within the image into the text box below it. This process is used to prevent automated spam bots.
Image Verification
(case insensitive)

Possibly Related Threads...
Thread Author Replies Views Last Post
  Unified Modeling Language (UML) computer science crazy 4 4,562 03-03-2012, 02:44 PM
Last Post: seminar paper
  ROBOTIC SURGERY AND TELE-SURGERY: BASIC PRINCIPLES AND DESCRIPTION OF A NOVEL CONCEPT projectsofme 1 2,855 27-02-2012, 01:12 PM
Last Post: seminar paper
  Email Based Hardware control full report seminar class 0 1,897 14-05-2011, 10:13 AM
Last Post: seminar class
  OWL Web Ontology Language computer science crazy 1 2,649 09-05-2011, 04:34 PM
Last Post: sdash
  SMIL- Synchronized Multimedia Integration Language seminar class 0 1,923 19-04-2011, 09:45 AM
Last Post: seminar class
  Introduction to 3D Graphics Hardware seminar class 0 1,744 14-04-2011, 03:35 PM
Last Post: seminar class
  XBL eXtensible Bindings Language computer science crazy 1 2,050 17-01-2011, 12:37 PM
Last Post: G Prathyusha
  An Algorithm for Language Independent Speaker Identification projectsofme 0 1,580 24-11-2010, 05:16 PM
Last Post: projectsofme
  JHDL (Java Hardware Description Language) computer science crazy 1 2,430 20-02-2010, 08:15 PM
Last Post: shankar.legend
  Resource Description Framework (RDF) computer science crazy 0 1,014 03-09-2009, 05:13 PM
Last Post: computer science crazy

Forum Jump: