Dear sirs
I want vhdl code of carry select adder with simulation in Modelsim.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity CSA is
Port ( x : in unsigned (3 downto 0);
y : in unsigned (3 downto 0);
z : in unsigned (3 downto 0);
cout : out std_logic;
s : out unsigned (4 downto 0)
);
end CSA;

architecture Behavioral of CSA is

component fulladder is
port (a : in std_logic;
b : in std_logic;
cin : in std_logic;
sum : out std_logic;
carry : out std_logic
);
end component;

signal c1,s1,c2 : unsigned (3 downto 0) := (others => '0');

begin

fa_inst10 : fulladder port map(x(0),y(0),z(0),s1(0),c1(0));
fa_inst11 : fulladder port map(x(1),y(1),z(1),s1(1),c1(1));
fa_inst12 : fulladder port map(x(2),y(2),z(2),s1(2),c1(2));
fa_inst13 : fulladder port map(x(3),y(3),z(3),s1(3),c1(3));

fa_inst20 : fulladder port map(s1(1),c1(0),c2(0),s(1),c2(1));
fa_inst21 : fulladder port map(s1(2),c1(1),c2(1),s(2),c2(2));
fa_inst22 : fulladder port map(s1(3),c1(2),c2(2),s(3),c2(3));
fa_inst23 : fulladder port map('0',c1(3),c2(3),s(4),cout);

s(0) <= s1(0);

end Behavioral;