interfacing ldr using vhdl with altera de2 board.

FPGA comes with different voltage IO standards. You have to select IO standard in your FPGA IO planning tool. Normally ADCs have Parallel interface for high speed and use SPI for low speed ADC. Parallel interface reads a clock from ADC and set of bus from ADC with respect to clock. The main constraint here is to offset your bus based on input clock (Setup your Input Flop). ADC datasheet will give you the relationship of the adc clock and it's output data. That should help you decide your setup requirements. If the ADC uses DDR interface, then you might want to use DDR primitive IO from your FPGA. However the IO standard shall remain same