Spring 2007 Class Project 32-Bit MIPS Microprocessor CMOS VLSI Design

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Microarchitecture Cluster
1. Introduction
Harvey Mudd College's Spring 2007 VLSI class decided to implement the MIPS ISA. This project required a microarchitecture specification written in Verilog. This report summarizes the implementation process and results.
2. Responsibilities
The Microarchitecture Team was broken up into the following roles.
2.1. Carl Nygaard - Chief Microarchitect
The responsibility of the Chief Microarchitect was to develop the overall design of the microprocessor and see to the implementation of the microprocessor in HDL. This included specifying and implementing the processor's instruction set as well as choosing and implementing various features.

4. Feature Set
4.1. Branch Delay Slot and Hazard Detection
The branch delay slot behavior of the MIPS I instruction set was duplicated. Hazard detection was also implemented to support various stalls and pipeline dependencies.
4.2. Memory and Cache System
4.2.1. Overview
The memory and cache system is composed of the following modules: Two identical 512 byte caches: one for data and one for instructions organized as SRAM. A write buffer to reduce number of stalls when writing to main memory. A memsys controller which multiplexes data between the above modules, processor, and external memory.
4.2.2. Memory Interface Conventions
All of the primary memory and cache system modules follow a common interface convention for control signals and address/data buses. The interface convention includes:
The Memory Microarchitect was responsible for designing the on-chip memory and cache system. This included designing and implementing the caches, a write buffer, and a module to arbitrate requests between all of the memory system modules, the processor, and the external memory. Multiple cycle latency test memory was implemented to aid in testing. Lastly, specifications for the memory and cache system were written.
2.3. Thomas Barr - Exception Microarchitect
The Exception Microarchitect was responsible for determining the behavior of the CPU on invalid operation and interrupts, and implementing the necessary hardware to deal with exceptions and interrupts. Several exceptions were required for debugging, system calls and allowing the system to recover from invalid programs and data. The nature of the CPU required that the hardware to do this be extremely efficient in order to fit in the given area. In addition, the exception microarchitect assisted the chief microarchitect in adapting the CPU HDL to be in structural form, and developed a synthesizable automatic test bench that allowed the creation of an automated tester alongside the CPU in and FPGA to rapidly verify the proper functionality of the chip.
2.4. Matt Totino - Validation Microarchitect
The responsibility of the Validation Microarchitect was to design and implement tests in addition to those developed by the other module designers for use in their regression testing. The additional tests checked implementation of required operations more extensively and gave specific attention to cases in which many different functions of the chip (for example, hazards, exceptions, and branching) were used together.