26-01-2012, 05:08 PM
DESIGNING COMBINATIONAL LOGIC GATES IN CMOS
[attachment=16679]
Introduction
The design considerations for a simple inverter circuit were presented in the previous
chapter. In this chapter, the design of the inverter will be extended to address the synthesis
of arbitrary digital gates such as NOR, NAND and XOR. The focus will be on combinational
logic (or non-regenerative) circuits that have the property that at any point in time,
the output of the circuit is related to its current input signals by some Boolean expression
(assuming that the transients through the logic gates have settled). No intentional connection
between outputs and inputs is present.
Static CMOS Design
The most widely used logic style is static complementary CMOS. The static CMOS style
is really an extension of the static CMOS inverter to multiple inputs. In review, the primary
advantage of the CMOS structure is robustness (i.e, low sensitivity to noise), good
performance, and low power consumption (with no static power consumption)
Complementary CMOS
A static CMOS gate is a combination of two networks, called the pull-up network (PUN)
and the pull-down network (PDN) (Figure 6.2). The figure shows a generic N input logic
gate where all inputs are distributed to both the pull-up and pull-down networks. The function
of the PUN is to provide a connection between the output and VDD anytime the output
of the logic gate is meant to be 1 (based on the inputs). Similarly, the function of the PDN
is to connect the output to VSS when the output of the logic gate is meant to be 0.
