04-12-2014, 10:56 PM
Please I need help on how to go about building a testbench for hamming code generator in VHDL. Thank you
vhdl test bench for hamming code generator
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Quote:library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
ENTITY hamming_encoder IS
PORT(datain : IN BIT_VECTOR(0 TO 3); --d0 d1 d2 d3
hamout : OUT BIT_VECTOR(0 TO 6)); --d0 d1 d2 d3 p0 p1 p2
END hamming_encoder;
ARCHITECTURE beh OF hamming_encoder IS
SIGNAL p0, p1, p2 : BIT; --check bits
BEGIN
--generate check bits
p0 <= (datain(0) XOR datain(1)) XOR datain(3);
p1 <= (datain(0) XOR datain(2)) XOR datain(3);
p2 <= (datain(1) XOR datain(2)) XOR datain(3);
--connect up outputs
hamout(4 TO 6) <= (p0, p1, p2);
hamout(0 TO 3) <= datain(0 TO 3);
END beh;
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