[attachment=14671]
Field Programmable Gate Arrays (FPGA)
CLB – Configurable Logic Block, contains RAM based Loop-Up-table (LUT) to implement Logic and storage element.
IOB – Input Output Block control the flow of data between the I/O and the internal Logic of the device.
Block RAM provides data storage in form of Dual Port RAM
Multiplier accepts two 18-number and outputs product.
DCM : Digital Clock Manager is used to generate clock with desired frequency and phase.
Advantages of FPGA
Very complicated design upto 5Million gates can be achieved with FPGAs.
Logic density in the FPGA is very high.
Internal RAM is included, which helps to develop SOC.
Complicated clocking scheme allowing upto 8 clock inputs, clk multiply, clk divide, phase shift etc.
Variety of I/O standards supported. LVTTL, LVCMOS, LVPECL, PCI, HSTL etc.
Disadvantages of FPGA
Additional Power consumption.
Slower than CPLD when it comes to pin-to-pin delay.
Volatile, requires a device to configure the FPGA everytime.