Pin configuration of 8085 and 8086 Microprocessors
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8085 PIN DESCRIPTION
Some important pins are :
• AD0-AD7: Multiplexed Address and data lines.
• A8-A15: Tri-stated higher order address lines.
• ALE: Address latch enable is an output signal. It goes high when operation is started by processor .
• S0,S1: These are the status signals used to indicate type of operation.
• RD¯: Read is active low input signal used to read data from I/O device or memory.
• WR¯:Write is an active low output signal used write data on memory or an I/O device.
• READY:This an output signal used to check the status of output device.If it is low, μP will WAIT until it is high.
• TRAP:It is an Edge triggered highest priority , non mask able interrupt. After TRAP, restart occurs and execution starts from address 0024H.
• RST5.5,6.5,7.5: These are maskable interrupts and have low priority than TRAP.
• INTR¯&INTA:INTR is a interrupt request signal after which μP generates INTA or interrupt acknowledge signal.
• IO/M¯:This is output pin or signal used to indicate whether 8085 is working in I/O mode(IO/M¯=1) or Memory mode(IO/M¯=0 ).
• HOLD&HLDA:HOLD is an input signal .When μP receives HOLD signal it completes current machine cycle and stops executing next instruction.In response to HOLD μP generates HLDA that is HOLD Acknowledge signal.
• RESET IN¯:This is input signal.When RESET IN¯ is low μp restarts and starts executing from location 0000H.
• SID: Serial input data is input pin used to accept serial 1 bit data .
• X1X2 :These are clock input signals and are connected to external LC,or RC circuit.These are divide by two so if 6 MHz is connected to X1X2, the operating frequency becomes 3 MHz.
• VCC&VSSower supply VCC=+ -5Volt& VSS=-GND reference.



MIN/MAX (minimum and maximum mode)- This signal represents two operation modes of the processor: minimum and maximum. When the signal is high (connected to +5v), the processor operates in minimum mode (Uniprocessor), and when it is low (grounded), the processor operates in maximum mode (multiprocessor). The minimum mode is used for the single processor environment, and maximum mode is used for the multiprocessor environment. In the maximum mode, eight pins (24-31) are assigned functions compared to that of minimum mode as shown in following table.


Bus structure
4.2.1 Synchronous Bus: In a synchronous bus, the occurrence of the events on the bus is determined by a clock. The clock transmits a regular sequence of a 0‘s and 1‘s of equal duration. A single 1-0 transmission is called clock cycle or bus cycle and defines a time slot. All other devices on the bus can read the clock live, and all events start at the beginning of the clock cycle. Let us consider the timing diagram for a synchronous read operation as shown in figure 4.2.1a