16-11-2010, 10:17 PM
1. INTRODUCTION
The Universal Asynchronous Receiver/Transmitter (UART) controller is the key component of the serial communications subsystem of a computer. The UART takes bytes of data and transmits the individual bits in a sequential fashion. At the destination, a second UART re-assembles the bits into complete bytes. Serial transmission of digital information (bits) through a single wire or other medium is much more cost effective than parallel transmission through multiple wires. A UART is used to convert the transmitted information between its sequential and parallel form at each end of the link. UARTs are commonly used with RS-232 for embedded systems communications.
RS232 is an asynchronous serial communication protocol widely used in computers and digital systems. In RS-232, user data is sent as a time-series of bits. Since transmit data and receive data are separate circuits, the interface can operate in a full duplex manner, supporting concurrent data flow in both directions. The standard does not define character framing within the data stream, or character encoding.
The keyboard is used to type text and numbers into a word processor, text editor or other program. A computer keyboard distinguishes each physical key from every other and reports all keypresses to the controlling software.
On PC's side, Windows' HyperTerminal program can be used as a virtual terminal to interact with the FPGA board.
A field programmable gate array is a logic device that contains a two-dimensional array of generic logic cells and programmable switches. A design can be implemented by specifying the function of each logic cell and selectively setting the connection of each programmable switch.
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The main objectives of this project includes
• keyboard interfacing
• UART interfacing
• FPGA programming
• Hyperterminal interaction
The different tools required in this programming are
• ModelSim SE 6.5
• Xilinx ISE 10.1
2.BLOCK DIAGRAM
3.KEYBOARD INTERFACING
The most popular keyboards in use today include:
• USB keyboard - Latest keyboard supported by all new computers (Macintosh and IBM/compatible). These are relatively complicated to interface and are not covered in this article.
• IBM/Compatible keyboards - Also known as "AT keyboards" or "PS/2 keyboards", all modern PCs support this device. They're the easiest to interface, and are the subject of this article.
• ADB keyboards - Connect to the Apple Desktop Bus of older Macintosh systems. These are not covered in this article.
Features of IBM PS/2 Keyboard (1987)
• 84 - 101 keys
• 6-pin mini-DIN connector
• Bi-direction serial protocol
• Offers optional scan code set 3
• 17 host-to-keyboard commands
The PS/2 keyboard was originally an extension of the AT device. It supported a few additional host-to-keyboard commands and featured a smaller connector. These were the only differences between the two devices. However, computer hardware has never been about standards as much as compatibility. For this reason, any keyboard you buy today will be compatible with PS/2 and AT systems, but it may not fully support all the features of the original devices.
Features of Modern PS/2 (AT) compatible keyboards
• Any number of keys (usually 101 or 104)
• 5-pin or 6-pin connector; adaptor usually included
• Bi-directional serial protocol
• Only scan code set 2 guaranteed.
• Acknowledges all commands; may not act on all of them.
Keyboards consist of a large matrix of keys, all of which are monitored by an on-board processor (called the "keyboard encoder".) The specific processor varies from keyboard-to-keyboard but they all basically do the same thing.Monitor which key(s) is being pressed/released and send the appropriate data to the host. This processor takes care of all the debouncing and buffers any data in its 16-byte buffer, if needed. Your motherboard contains a "keyboard controller" that is in charge of decoding all of the data received from the keyboard and informing your software of what's going on. All communication between the host and the keyboard uses an IBM protocol.
PS2 port was introduced in IBM’s Personal Systed2 personnel computers. It is a widely supported interface for a keyboard and mouse to communicate with the host. The PS2 port contains two wires for communication purposes. One wire is for data, which is transmitted in a serial stream. The other wire is for the clock information, which specifies when the data is valid and can be retrieved. The information is transmitted as an 1 1-bit “packet” that contains a start bit, 8 data bits, an odd parity bit, and a stop bit. Whereas the basic format of the packet is identical for a keyboard and a mouse, the interpretation for the data bits is different. The FPGA prototyping board has a PS2 port and acts as a host.
The communication of the PS2 port is bi-directional and the host can send a command to the keyboard or mouse to set certain parameters. For our purposes, the bi-directional communication is hardly required for the PS2 keyboard, and thus our discussion is limited to one direction, from the keyboard to the prototyping board.
3.1 PS2 RECEIVING SUBSYSTEM
In addition to data and clock lines, the PS2 port includes connections for power (i.e., Vcc) and ground. The power is supplied by the host. In the original PS2 port, V,, is 5 V and the outputs of the data and clock lines are open-collector. However, most current keyboards and mice can work well with 3.3 V. For an older keyboard and mouse, the 5-V supply can be obtained by switching the 52 jumper on the S3 board. The FPGA should still function properly since its I/O pins can tolerate 5-V input.
3.1.1 Device-to-host communication protocol
A PS2 device and its host communicate via packets. The basic timing diagram of transmitting a packet from a PS2 device to a host is shown in Figure 8.1, in which the data and clock signals are labeled ps2d and ps2c, respectively. The data is transmitted in a serial stream, and its format is similar to that of a UART. Transmission begins with a start bit, followed by 8 data bits and an odd parity bit, and ends with a stop bit. Unlike a UART, the clock information is carried in a separate clock signal, ps2c. The falling edge of the ps2c signal indicates that the corresponding bit in the ps2d line is valid and can be retrieved. The clock period of the ps2c signal is between 60 and 100 ps (i.e., 10 kHz to 16.7 kHz), and the ps2d signal is stable at least 5 ps before and after the falling edge of the ps2c signal.
3.1.2 Design and code
The design of the PS2 port receiving subsystem is somewhat similar to that of a UART receiver. Instead of using the oversampling scheme, the falling-edge of the ps2c signal is used as the reference point to retrieve data. The subsystem includes a falling edge detection circuit, which generates a one-clock-cycle tick at the falling edge of the ps2c signal, and the receiver, which shifts in and assembles the serial bits.
3.2 PS2 KEYBOARD SCAN CODE
3.2.1 Overview of the scan code
A keyboard consists of a matrix of keys and an embedded microcontroller that monitors (i.e., scans) the activities of the keys and sends scan code accordingly. Three types of key activities are observed:
• When a key is pressed, the make code of the key is transmitted.
• When a key is held down continuously, a condition known as typematic, the make
code is transmitted repeatedly at a specific rate. By default, a PS2 keyboard transmits the make code about every 100 ms after a key has been held down for 0.5 second.
• When a key is released, the break code of the key is transmitted.
The make code of the main part of a PS2 keyboard is shown in Figure 8.3. It is normally 1 byte wide and represented by two hexadecimal numbers. For example, the make code of the A key is 1C. This code can be conveyed by one packet when transmitted. The make codes of a handful of special-purpose keys, which are known as the extended keys, can have 2 to 4 bytes.
For example, the make code of the upper arrow on the right is EO 75. Multiple packets are needed for the transmission. The break codes of the regular keys consist of FO followed by the make code of the key.
For example, the break code of the A key is FO 1C. The PS2 keyboard transmits a sequence of codes according to the key activities. For example, when we press and release the A key, the keyboard first transmits its make code and then the break code:
1C FO 1C
If we hold the key down for awhile before releasing it, the make code will be transmitted multiple times:
1C 1C 1 C . . . 1C FO 1 C
Multiple keys can be pressed at the same time. For example, we can first press the shift Key (whose make code is 12) and then the A key, and release the A key and then release the shift key. The transmitted code sequence follows the make and break codes of the two Keys:
12 1 C FO 1 C FO 12
The previous sequence is how we normally obtain an uppercase A. Note that there is nospecial code to distinguish the lower- and uppercase keys. It is the responsibility of thehost device to keep track of whether the shift key is pressed and to determine the case
accordingly.
3.2.2 Scan code monitor circuit
The scan code monitor circuit monitors the arrival of the received packets and displays the scan codes on a PC's HyperTerminal window. The basic design approach is to first split the received scan code into two 4-bit parts and treat them as two hexadecimal digits, and then convert the two digits to ASCII code words and send the words to a PC via the UART.
The UART operation is initiated when a new scan code is received (as indicated by the assertion of scan-done-tick). The FSM circulates through the s e n d l , send0, and sendb states, in which the ASCII codes of the upper hexadecimal digit, lower hexadecimal digit, and blank space are written to the UART.
3.2.3 Scan Codes
Keyboard's processor spends most of its time "scanning", or monitoring, the matrix of keys. If it finds that any key is being pressed, released, or held down, the keyboard will send a packet of information known as a "scan code" to the computer. There are two different types of scan codes: "make codes" and "break codes". A make code is sent when a key is pressed or held down. A break code is sent when a key is released. Every key is assigned its own unique make code and break code so the host can determine exactly what happened to which key by looking at a single scan code. The set of make and break codes for every key comprises a "scan code set". There are three standard scan code sets, named one, two, and three.
3.2.4 Make Codes, Break Codes, and Typematic Repeat:
Whenever a key is pressed, that key's make code is sent to the computer. A make code only represents a key on a keyboard it does not represent the character printed on that key. This means that there is no defined relationship between a make code and an ASCII code. It's up to the host to translate scan codes to characters or commands.
Although most set two make codes are only one-byte wide, there are a handful of "extended keys" whose make codes are two or four bytes wide. These make codes can be identified by the fact that their first byte is E0h.
Just as a make code is sent to the computer whenever a key is pressed, a break code is sent whenever a key is released. In addition to every key having its own unique make code, they all have their own unique break code. Fortunately, however, you won't always have to use lookup tables to figure out a key's break code--certain relationships do exist between make codes and break codes. Most set two break codes are two bytes long where the first byte is F0h and the second byte is the make code for that key. Break codes for extended keys are usually three bytes long where the first two bytes are E0h, F0h, and the last byte is the last byte of that key's make code.
If you press a key, its make code is sent to the computer. When you press and hold down a key, that key becomes typematic, which means the keyboard will keep sending that key's make code until the key is released or another key is pressed. To verify this, open a text editor and hold down the "A" key. When you first press the key, the character "a" immediately appears on your screen. After a short delay, another "a" will appear followed by a whole stream of "a"s until you release the "A" key. There are two important parameters here: the typematic delay, which is the short delay between the first and second "a", and the typematic rate, which is how many characters per second will appear on your screen after the typematic delay. The typematic delay can range from 0.25 seconds to 1.00 second and the typematic rate can range from 2.0 cps (characters per second) to 30.0 cps. You may change the typematic rate and delay using the "Set Typematic Rate/Delay" (0xF3) command.
Typematic data is not buffered within the keyboard. In the case where more than one key is held down, only the last key pressed becomes typematic. Typematic repeat then stops when that key is released, even though other keys may be held down.
3.3 Keyboard Interface Signaling
The interface between the keyboard and the keyboard controller on the motherboard is really a communications channel, over which commands and data are passed. The keyboard interface uses specific signaling protocols and standards to ensure that pretty much any keyboard can talk to any PC system.
The standard keyboard interface is a serial communications link. "Serial" just means that data is sent one bit at a time over a single line (as opposed to parallel channels, where many bits are sent at once over many lines). Serial communications was chosen for the keyboard interface because it is simple and reliable, and not a lot of data per second needs to be sent over the interface for a keyboard.
There are four lines that comprise the channel between the PC and the keyboard. Two of these, the power and ground lines, are used to provide power to the keyboard. The other two are these signaling lines:
• Keyboard Data: This is the line over which data bits are sent to the system from the keyboard, and commands sent from the system to the keyboard.
• Keyboard Clock: This is a repetitive, regular clock signal, with a value that switches from 1 to 0 to 1 to 0 in a regular pattern. It is much like the ones used elsewhere in the PC, such as to control the system memory, or the expansion bus. Of course, it runs much slower than these other clocks, since the keyboard is a slow device. The purpose of the clock signal is to synchronize the keyboard and the system, so they are always "on the same page" regarding exactly when data will show up on the keyboard data signal line.
Though the keyboard interface is similar to a regular PC serial communications line, the presence of the clock signal really differentiates the two. The clock makes the keyboard signaling synchronous; all bit transfers occur in time with the beat of the clock, almost like a drummer setting the tone for a band. Conventional serial connections are asynchronous; the data is sent not based on a clock but in response to a specific request from one device or the other.
3.4 Keyboard Keys and Key Code Values
The following tables list all the keys on a standard keyboard and the corresponding key code values and ASCII key code values that are used to identify the keys in Action Script:
• Letters A to Z and standard numbers 0 to 9
• Keys on the numeric keypad
• Function keys
• Other keys
Letters A to Z and standard numbers 0 to 9
The following table lists the keys on a standard keyboard for the letters A to Z and the numbers 0 to 9, with the corresponding key code values that are used to identify the keys in Action Script:
Letter or number key Key code ASCII key code
A 65 65
B 66 66
C 67 67
D 68 68
E 69 69
F 70 70
G 71 71
H 72 72
I 73 73
J 74 74
K 75 75
L 76 76
M 77 77
N 78 78
O 79 79
P 80 80
Q 81 81
R 82 82
S 83 83
T 84 84
U 85 85
V 86 86
W 87 87
X 88 88
Y 89 89
Z 90 90
0 48 48
1 49 49
2 50 50
3 51 51
4 52 52
5 53 53
6 54 54
7 55 55
8 56 56
9 57 57
a 65 97
b 66 98
c 67 99
d 68 100
e 69 101
f 70 102
g 71 103
h 72 104
i 73 105
j 74 106
k 75 107
l 76 108
m 77 109
n 78 110
o 79 111
p 80 112
q 81 113
r 82 114
s 83 115
t 84 116
u 85 117
v 86 118
w 87 119
x 88 120
y 89 121
z 90 122
3.4.1 Keys on the numeric keypad
The following table lists the keys on a numeric keypad, with the corresponding key code values that are used to identify the keys in ActionScript:
Numeric keypad key Key code ASCII key code
Numpad 0 96 48
Numpad 1 97 49
Numpad 2 98 50
Numpad 3 99 51
Numpad 4 100 52
Numpad 5 101 53
Numpad 6 102 54
Numpad 7 103 55
Numpad 8 104 56
Numpad 9 105 57
Multiply 106 42
Add 107 43
Enter 13 13
Subtract 109 45
Decimal 110 46
Divide 111 47
3.4.2 Function keys
The following table lists the function keys on a standard keyboard, with the corresponding key code values that are used to identify the keys in ActionScript:
Function key Key code ASCII key code
F1 112 0
F2 113 0
F3 114 0
F4 115 0
F5 116 0
F6 117 0
F7 118 0
F8 119 0
F9 120 0
F10 This key is reserved by the system and cannot be used in ActionScript. This key is reserved by the system and cannot be used in ActionScript.
F11 122 0
F12 123 0
F13 124 0
F14 125 0
F15 126 0
3.4.3 Other keys
The following table lists keys on a standard keyboard other than letters, numbers, numeric keypad keys, or function keys, with the corresponding key code values that are used to identify the keys in ActionScript:
Key Key code ASCII key code
Backspace 8 8
Tab 9 9
Enter 13 13
Shift 16 0
Control 17 0
Caps Lock 20 0
Esc 27 27
Spacebar 32 32
Page Up 33 0
Page Down 34 0
End 35 0
Home 36 0
Left Arrow 37 0
Up Arrow 38 0
Right Arrow 39 0
Down Arrow 40 0
Insert 45 0
Delete 46 127
Num Lock 144 0
ScrLk 145 0
Pause/Break 19 0
; : 186 59
= + 187 61
- _ 189 45
/ ? 191 47
` ~ 192 96
[ { 219 91
\ | 220 92
] } 221 93
" ' 222 39
, 188 44
. 190 46
/ 191 47
4. UART INTERFACING
A universal asynchronous receiver/transmitter (usually abbreviated UART )is a type of "asynchronous receiver/transmitter", a piece of computer hardware that translates data between parallel and serial forms. UARTs are commonly used in conjunction with other communication standards such as EIA RS-232.
A UART is usually an individual (or part of an) integrated circuit used for serial communications over a computer or peripheral device serial port. UARTs are now commonly included in microcontrollers. A dual UART or DUART combines two UARTs into a single chip.
The Serial Port is harder to interface than the Parallel Port. In most cases, any device you connect to the serial port will need the serial transmission converted back to parallel so that it can be used. This can be done using a UART.
A UART is a chip with programming that controls a computers interface to its attached serial devices.On older computers the chips were on the disk 10 controller card.
The UART’s purpose is to convert bytes from PC’s parallel bus to a serial bit stream. The cable going out of the serial port is serial and has only one wire for each direction of flow.The serial port sends out a stream of bits, one bit at a time.Conversly, the bit stream that enters the serial port via the external cable is converted to parallel bytes that the computer can understand.UART deals with the data in byte sized pieces, which is conveniently also the size of ASCII characters.
Specifically it provides the computer with the RS-232C DTE interface so that it can talk to and exchange data with modems and other serial devices. As a part of this interface, the UART also converts the bytes it receives from the computer along the parallel circuits into a single serial bit stream for outbound transmission.
4.1 Transmitting and receiving serial data
The Universal Asynchronous Receiver/Transmitter (UART) controller is the key component of the serial communications subsystem of a computer. The UART takes bytes of data and transmits the individual bits in a sequential fashion. At the destination, a second UART re-assembles the bits into complete bytes. Serial transmission of digital information (bits) through a single wire or other medium is much more cost effective than parallel transmission through multiple wires. A UART is used to convert the transmitted information between its sequential and parallel form at each end of the link. Each UART contains a shift register which is the fundamental method of conversion between serial and parallel forms.
The UART usually does not directly generate or receive the external signals used between different items of equipment. Typically, separate interface devices are used to convert the logic level signals of the UART to and from the external signaling levels.
External signals may be of many different forms. Examples of standards for voltage signaling are RS-232, RS-422 and RS-485 from the EIA.
UARTs are commonly used with RS-232 for embedded systems communications. It is useful to communicate between microcontrollers and also with PCs. Many chips provide UART functionality in silicon, and low-cost chips exist to convert logic level signals (such as TTL voltages) to RS-232 level signals (for example, Maxim's MAX232).
4.2 Synchronous Serial Transmission
Synchronous serial transmission requires that the sender and receiver share a clock with one another, or that the sender provide a strobe or other timing signal so that the receiver knows when to “read” the next bit of the data. In most forms of serial Synchronous communication, if there is no data available at a given instant to transmit, a fill character must be sent instead so that data is always being transmitted. Synchronous communication is usually more efficient because only data bits are transmitted between sender and receiver, and synchronous communication can be more costly if extra wiring and circuits are required to share a clock signal between the sender and receiver.
A form of Synchronous transmission is used with printers and fixed disk devices in that the data is sent on one set of wires while a clock or strobe is sent on a different wire. Printers and fixed disk devices are not normally serial devices because most fixed disk interface standards send an entire word of data for each clock or strobe signal by using a separate wire for each bit of the word. In the PC industry, these are known as Parallel devices.
The standard serial communications hardware in the PC does not support Synchronous operations. This mode is described here for comparison purposes only.
4.3 Asynchronous Serial Transmission
Asynchronous transmission allows data to be transmitted without the sender having to send a clock signal to the receiver. Instead, the sender and receiver must agree on timing parameters in advance and special bits are added to each word, which are used to synchronize the sending and receiving units.
When a word is given to the UART for Asynchronous transmissions, a bit called the "Start Bit" is added to the beginning of each word that is to be transmitted. The Start Bit is used to alert the receiver that a word of data is about to be sent, and to force the clock in the receiver into synchronization with the clock in the transmitter. These two clocks must be accurate enough to not have the frequency drift by more than 10% during the transmission of the remaining bits in the word.
After the Start Bit, the individual bits of the word of data are sent, with the Least Significant Bit (LSB) being sent first. Each bit in the transmission is transmitted for exactly the same amount of time as all of the other bits, and the receiver “looks” at the wire at approximately halfway through the period assigned to each bit to determine if the bit is a 1 or a 0. For example, if it takes two seconds to send each bit, the receiver will examine the signal to determine if it is a 1 or a 0 after one second has passed, then it will wait two seconds and then examine the value of the next bit, and so on.
The sender does not know when the receiver has “looked” at the value of the bit. The sender only knows when the clock says to begin transmitting the next bit of the word.
When the entire data word has been sent, the transmitter may add a Parity Bit that the transmitter generates. The Parity Bit may be used by the receiver to perform simple error checking. Then at least one Stop Bit is sent by the transmitter.
When the receiver has received all of the bits in the data word, it may check for the Parity Bits (both sender and receiver must agree on whether a Parity Bit is to be used), and then the receiver looks for a Stop Bit. If the Stop Bit does not appear when it is supposed to, the UART considers the entire word to be garbled and will report a Framing Error to the host processor when the data word is read. The usual cause of a Framing Error is that the sender and receiver clocks were not running at the same speed, or that the signal was interrupted.
Regardless of whether the data was received correctly or not, the UART automatically discards the Start, Parity and Stop bits. If the sender and receiver are configured identically, these bits are not passed to the host.
If another word is ready for transmission, the Start Bit for the new word can be sent as soon as the Stop Bit for the previous word has been sent.
Because asynchronous data is “self synchronizing”, if there is no data to transmit, the transmission line can be idle.
4.4 Bits, Baud and Symbols
Baud is a measurement of transmission speed in asynchronous communication. Because of advances in modem communication technology, this term is frequently misused when describing the data rates in newer devices.
Traditionally, a Baud Rate represents the number of bits that are actually being sent over the media, not the amount of data that is actually moved from one DTE device to the other. The Baud count includes the overhead bits Start, Stop and Parity that are generated by the sending UART and removed by the receiving UART. This means that seven-bit words of data actually take 10 bits to be completely transmitted. Therefore, a modem capable of moving 300 bits per second from one place to another can normally only move 30 7-bit words if Parity is used and one Start and Stop bit are present.
If 8-bit data words are used and Parity bits are also used, the data rate falls to 27.27 words per second, because it now takes 11 bits to send the eight-bit words, and the modem still only sends 300 bits per second.
The formula for converting bytes per second into a baud rate and vice versa was simple until error-correcting modems came along. These modems receive the serial stream of bits from the UART in the host computer (even when internal modems are used the data is still frequently serialized) and converts the bits back into bytes. These bytes are then combined into packets and sent over the phone line using a Synchronous transmission method. This means that the Stop, Start, and Parity bits added by the UART in the DTE (the computer) were removed by the modem before transmission by the sending modem. When these bytes are received by the remote modem, the remote modem adds Start, Stop and Parity bits to the words, converts them to a serial format and then sends them to the receiving UART in the remote computer, who then strips the Start, Stop and Parity bits.
The reason all these extra conversions are done is so that the two modems can perform error correction, which means that the receiving modem is able to ask the sending modem to resend a block of data that was not received with the correct checksum. This checking is handled by the modems, and the DTE devices are usually unaware that the process is occurring.
By striping the Start, Stop and Parity bits, the additional bits of data that the two modems must share between themselves to perform error-correction are mostly concealed from the effective transmission rate seen by the sending and receiving DTE equipment. For example, if a modem sends ten 7-bit words to another modem without including the Start, Stop and Parity bits, the sending modem will be able to add 30 bits of its own information that the receiving modem can use to do error-correction without impacting the transmission speed of the real data.
The use of the term Baud is further confused by modems that perform compression. A single 8-bit word passed over the telephone line might represent a dozen words that were transmitted to the sending modem. The receiving modem will expand the data back to its original content and pass that data to the receiving DTE.
Modern modems also include buffers that allow the rate that bits move across the phone line (DCE to DCE) to be a different speed than the speed that the bits move between the DTE and DCE on both ends of the conversation. Normally the speed between the DTE and DCE is higher than the DCE to DCE speed because of the use of compression by the modems.
Because the number of bits needed to describe a byte varied during the trip between the two machines plus the differing bits-per-seconds speeds that are used present on the DTE-DCE and DCE-DCE links, the usage of the term Baud to describe the overall communication speed causes problems and can misrepresent the true transmission speed. So Bits Per Second (bps) is the correct term to use to describe the transmission rate seen at the DCE to DCE interface and Baud or Bits Per Second are acceptable terms to use when a connection is made between two systems with a wired connection, or if a modem is in use that is not performing error-correction or compression.
Modern high speed modems (2400, 9600, 14,400, and 19,200bps) in reality still operate at or below 2400 baud, or more accurately, 2400 Symbols per second. High speed modem are able to encode more bits of data into each Symbol using a technique called Constellation Stuffing, which is why the effective bits per second rate of the modem is higher, but the modem continues to operate within the limited audio bandwidth that the telephone system provides. Modems operating at 28,800 and higher speeds have variable Symbol rates, but the technique is the same.
5.FPGA
A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by the customer or designer after manufacturing, hence "field-programmable". The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an application-specific integrated circuit (ASIC). FPGAs can be used to implement any logical function that an ASIC could perform. The ability to update the functionality after shipping, and the low non-recurring engineering costs relative to an ASIC design (not withstanding the generally higher unit cost), offer advantages for many applications.
FPGAs contain programmable logic components called "logic blocks", and a hierarchy of reconfigurable interconnects that allow the blocks to be "wired together"somewhat like a one-chip programmable breadboard. Logic blocks can be configured to perform complex combinational functions, or merely simple logic gates like AND and XOR. In most FPGAs, the logic blocks also include memory elements, which may be simple flip-flops or more complete blocks of memory.
5.1 FPGA Design
FPGA stands for Field Programmable Gate Array. There are many forms of devices which are field programmable. These are PAL, PLD, CPLD, and FPGA. These devices differ on their granularity, how the programming is accomplished etc. PAL, PLA and CPLD devices are usually smaller in capacity but more predictable in timing and they can be implemented with Sum-of-Products, Product-of-Sums or both. FPGA devices can be based on Flash, SRAM, EEPROM or Anti-Fuse connectivity. The most successful FPGA devices are based on SRAM. This is because all other memory types are much less dense in terms of area than SRAM. Also some types of connectivity are One-Time Programmable (i.e. Anti-Fuse) so they are not very flexible. SRAM based FPGAs have no maximum erase cycle limitations either.
FPGA development is in some sense similar to ASIC development. One can talk about Front-End Tools, which can be Schematic Entry or an HDL (Hardware Description Language). Most common HDLs used for FPGA Design are Verilog and VHDL. After describing an FPGA design in an HDL, a tool called a Synthesizer, which effectively converts Verilog, VHDL into the specific primitives, which exist an FPGA family. SRAM based FPGAs have Lookup-Tables which can be programmed to implement any function of N variables (usually 4~5) and Flip-Flops which can be programmed to implement different types of storage (JK, T, Latch, DFF with set and/or reset etc).
After a device level net list is generated with synthesis, one uses a back-end tool called Place & Route, which is most of the time supplied by the device vendor (i.e. Xilinx or Altera).
From the P&R tool, one obtains a file, which can be used to download onto an FPGA to program it with the hardware design described by the original HDL code. This download can be either done through a serial connection, a JTAG cable or programmed into a ROM and loaded into the FPGA every time power is applied. This is very roughly the flow of FPGA development.
5.2 Spartan-3A/3AN FPGA Starter Kit Board
5.2.1Introduction and Overview
The design stored in external Flash exercises the various I/O devices, such as the VGA display and serial ports. In addition it demonstrates new FPGA features, such as selectable MultiBoot and the power-saving Suspend mode.
1. Double-check the position of the board jumpers, as shown in Figure .These settings are required for the demonstration design to configure correctly.
2. Optionally connect a VGA display device. The display device can be a CRT, a flatpanel, or even a projector.
3. Optionally connect headphones or amplified speakers to the audio jack.
4. Set the SUSPEND switch to the “RUN” position.
5. Connect the included AC adapter to wall power and also to the board. The AC adapter
also includes attachments to support worldwide locals.
6. Turn on the power switch.
7. The character LCD and VGA display, if connected, display various informational
messages and instructions. If an audio device is connected, the board offers words of
welcome in a variety of languages.
8. Use the rotary/push-button switch to control various board functions.
9. Optionally connect a PS/2-style keyboard to support one of the included
demonstrating designs.
10. Optionally connect a PC directly to the board using a standard 9-pin serial cable.
5.2.2 Clock sources
The Spartan®-3A/3AN FPGA Starter Kit board supports three primary clock input
Sources, as shown in Figure.3-1
• The board includes an on-board 50 MHz clock oscillator.
• Clocks can be supplied off-board via an SMA-style connector. Alternatively, the FPGA can generate clock signals or other high-speed signals on the SMA-style connector.
• A 133 MHz clock oscillator is installed in the CLK_AUX socket. Optionally substitute a separate eight-pin DIP-style clock oscillator in the provided socket.
Clock Connections
Each of the clock inputs connect directly to a global buffer input. As shown in Table ,each of the clock inputs also optimally connects to an associated DCM. Only the CLK_AUX or the CLK_SMA input can use the associated DCM at any time.
However, both inputs are available as clock inputs.
50 MHz On-Board Oscillator
The board includes a 50 MHz oscillator with a 40% to 60% output duty cycle. The oscillator is accurate to ±2500 Hz or ±50 ppm.
Auxiliary Clock Oscillator Socket
A 133 MHz clock oscillator is installed in the auxiliary clock oscillator socket. The provided eight-pin socket accepts clock oscillators that fit the eight-pin DIP (8DIP) footprint. Substitute the oscillator in this socket if the FPGA application requires a frequency other than 50 MHz or 133 MHz. Alternatively, use the FPGA’s Digital Clock Manager (DCM) to generate or synthesize other frequencies from the on-board 50 MHz or 133 MHz oscillator.
SMA Clock Input or Output Connector
To provide a clock from an external source, connect the input clock signal to the SMA connector. The FPGA can also generate a single-ended clock output or other high-speed signal on the SMA clock connector for an external device.
5.2.3 RS-232 Serial Ports
As shown in Figure, the Spartan®-3A/3AN FPGA Starter Kit board has two RS-232 serial ports: a female DB9 DCE connector and a male DB9 DTE connector. The DCE-style port connects directly to the serial port connector available on most personal computers and workstations via a standard straight-through serial cable. For typical applications, the board does not require null modem cables, gender changers, or crossover cables. Use the DTE-style connector to control other RS-232 peripherals, such as modems or printers, or perform simple loopback testing with the DCE connector
Figure shows the connection between the FPGA and the two DB9 connectors. The FPGA supplies serial output data using LVTTL or LVCMOS levels to the Maxim device, which in turn, converts the logic value to the appropriate RS-232 voltage level. Likewise,the Maxim device converts the RS-232 serial input data to LVTTL levels for the FPGA. A series resistor between the Maxim output pin and the FPGA’s RXD pin protects against inadvertent logic conflicts such as accidentally connecting the board using a null-modem cable. In this example, both the FPGA and the external serial device are driving data on the transmit line.
5.2.4 PS/2 Mouse/Keyboard Port
The Spartan®-3A/3AN FPGA Starter Kit board includes a PS/2 mouse/keyboard port and the standard six-pin mini-DIN connector, labeled J28 on the board. Figure shows the PS/2 connector, and Table shows the signals on the connector. Use the primary connections indicated to connect a mouse or keyboard directly to the board
The PS/2 port I/Os should always be set to LVCMOS33 with the PULLUP attribute set true when used. If this attribute is not set, the voltage on the PS/2 I/Os will be greater than the maximum specified permissible amount in the data sheet. These I/Os can be damaged if the bitstream option for unused I/Os is set to float and the FPGA design is not using the PS/2 port pins. Both a PC mouse and keyboard use the two-wire PS/2 serial bus to communicate with a host device, the FPGA in this case. The PS/2 bus includes both clock and data.
Both a mouse and keyboard drive the bus with identical signal timings, and both use 11-bit words that include a start, a stop, and an odd parity bit. However, the data packets are organized differently for a mouse and keyboard. Both the keyboard and mouse interfaces allows bidirectional data transfers. For example, the FPGA host design can illuminate the state LEDs on the keyboard or change the communicate rate with the mouse. The PS/2 bus timing appears in Table 8-2 and Figure 8-2. The clock and data signals are only driven when data transfers occur; otherwise they are held in the idle state at a logic High. The timing defines signal requirements for mouse-to-host communications and bi-directional keyboard communications. As shown in Figure 8-2, the attached keyboard or mouse writes a bit on the data line when the clock signal is High, and the host reads the data line when the clock signal is Low.
6. HYPER TERMINAL INTERACTION
HyperTerminal is a communications program that is included free with Windows 95 and later. Although the program has some quirks, it's handy for sending data to serial displays. This tip sheet shows how to configure the program, and lists some known peculiarities.
HyperTerminal’s publisher, Hilgraeve, offers free and low-cost upgrades to the program, as well as more advanced communication software.
6.1 Setting up HyperTerminal
In a normal installation of Windows 95 or later, HyperTerminal is automatically installed under Programs: Accessories, so you access it as follows:
• Click Start
• Select Program
• Select Accessories
• Select HyperTerminal folder
o Select Hypertrm.exe
Upon launching HyperTerminal, you'll be given the opportunity to name and assign an icon to your settings. You may choose any name/icon. Afterwards, a series of dialog boxes will appear. Enter the following settings:
Phone Number
• Click the drop-down arrow by Connect Using
• Select Direct to COM1 (or 'direct to' the port you intend to use)
• Click OK
COM1 Properties, Port Settings
• Bits per Second: select 9600 (or desired baud rate)
• Data Bits: select 8
• Parity: select None
• Stop Bits: select 1
• Flow Control: select none
• Click OK
Advanced
• Select Defaults
• Click OK
• Click OK
This will get you into the main HyperTerminal window. There are still a few more settings to make. Pull down the File menu and select Properties.
Properties Dialog
• Click Settings tab
• Check Terminal Keys
• Set Emulation to Auto Detect
• Click ASCII Setup button
• Under ASCII Sending, check Echo typed characters locally
• Under ASCII Receiving, check Append line feeds to incoming line ends
• Click OK
6.2 Using HyperTerminal
Once you've configured the program, make sure to save your configuration for reuse. If you launch the program using your configuration icon, your settings will be loaded automatically.
With the settings listed above, anything you type into the HyperTerminal window will be sent out the serial port. You can also send most control characters by holding down the Ctrl key and typing the appropriate letter. For example, control-L (form feed) is recognized by our BPP-, BGX-, VFD-, and SGX-series displays as a clear-screen instruction. Hold Ctrl and type L to clear the LCD screen.
You can also use an old DOS trick to send particular ASCII values that may not have control-key equivalents. Hold down the Alt key and type the decimal ASCII value on the keyboard's numeric keypad (not the number keys along the top of the keyboard), then release Alt. Precede the number with a 0 (zero). For example, to send ASCII 133, press and hold Alt, type 0 1 3 3 on the keypad, then release Alt.
Don't leave out the 0 (zero) preceding the number! If you do, the actual value sent can be changed in odd ways. For example, ASCII 14 sent as Alt-down 1 4 Alt-up works fine, but ASCII 15 sent as Alt-down 1 5 Alt-up gets translated to ASCII 164.
The smart customer who pointed out the necessity of the leading zero speculates that it has to do with Windows' conversion of character codes to the DOS character set.
6.3 Corrupted Config Files
Saved configurations can be corrupted in odd ways. The most obvious symptom is that typing the same character three times in a row causes the third instance of the character to be sent incorrectly. In other cases, the terminal program fails to work altogether. The only fix we know of is to create a new configuration from scratch, as described above.
7. VHDL
7.1 INTRODUCTION
VHDL is a language for describing digital systems. It arose out of the US governments Very High Speed Integrated Circuits (VHSIC) program. In the course of this program, It became clear that there was need for a standard language for describing the structure and function of integrated circuits (ICs).hence the VHSIC Hardware Descriptive Language (VHDL) was developed. It was subsequently developed further under the auspices of the Institute Of Electrical and Electronics Engineers (IEEE) an adopted in the form of the IEEE standard 1076 standard HDL language reference manual in 1987.
The designers to describe the structure or behavior of digital system for simulation or synthesis mainly uses HDLs. An analogy of using VHDL for software design can be made to the history o using High Level Programming Language for software design, where it starts from machine code, to assembly language(schematic) and to High Level Language(HDL).
7.2 LEVELS OF ABSTRACTION
VHDL enables the description of a digital design at different levels of abstractions such as algorithmic, register transfer and logic gate level. A user can abstract a design or hide implementation details of a design using VHDL. In a top down design methodology, a designer usually represents the systems in high level abstraction first and later converts it to a more detailed design.
7.3 SIMULATION
A design description written in VHDL is usually run through a VHDL simulator to verify the behavior of the modeled system. To simulate a design, the designer must be supplied the simulator with set o stimuli. The simulation program applies the stimuli to the input description to the specified times and generates the responses of the circuit. The waveforms, timing diagrams or tabular listings may illustrate the result of the simulation program. The designer verifies whether or not the design process.
At a higher level of design process, simulation provides information regarding the functionality of the system under design. Normally the simulation of this level is very quick, but doesn’t provide the detailed information about the circuit functionality and timing. As a design process, goes down to the lower level of the design process, runs more slowly, but provides more detailed information about the timing and functionality of the circuits. VHDL allows mixed level design in which some of the modules are described in a high level of abstraction and some in lower level of abstraction. To avoid the higher cost of low level simulation runs, simulator should be used to detect the design flow as early as possible.
7.4 MODELLING LANGUAGE: VHDL
The building blocks of VHDL language are called design units. The five main design units are:
• Entity declaration
• Architecture body
• Configuration declaration
• Package declaration
• Package body
The description of the module in a digital system can be divided into external view and internal view. The external view describes the interface to the module including the number and the types of inputs and the types of outputs. The internal view describes how the module implements its function. In VHDL we can separate the description of the module into an entity declaration, which describes the external interface and one or more architecture bodies, which describes alternative internal implementations.
7.5 ENTITY DECLARATION
A digital system is usually designed as a hierarchical collection of modules. Each module has a set of ports, which constitutes its interface to the outside world in VHDL, an entity is such a module which may be used as a component in a design, or which may be the top level module of the design. The entity declarative part may be used to declare items, which are to be used in the implementation in the entity.
7.6 ARCHITECTURE DECLARATION
Once an entity has had its interface specified in an entity declaration, one or more implementations of the entity can be declared in architecture body. Each architecture body can describe a different view of the entity. For example, one architecture body may purely describe the behavior where as others may describe the structure of the entity as a hierarchically composed collection of components. The declaration in the architecture body defines items that will be used to construct the design description. In particular, signals and components may be declared here and used to construct a structural description in terms of component instances.
7.7 STRUCTURAL STYLE OF MODELLING
A digital electronics system can be described as a module with inputs and / outputs. The electrical values on the outputs are some function of the values on the inputs. The module F has two inputs A and B and output Y. using VHDL terminology, we call the module F a design entity, and the inputs and outputs are called ports. One way of describing the function of a module is to describe how it is composed of sub modules .Each of the sub modules is an instance of some entity, and the ports of the instances are connected using signals. The entity F might be composed of instances of entities G, H , I. This kind of description is called structural description.
7.8 DATAFLOW STYLE OF MODELING
In this type of modeling style the flow of data entity is expressed primarily using signal assignment statements. The structure of the entity is not explicitly specified but it can be implicitly deduced in this modeling style.
7.9 BEHAVIOURAL STYLE OF MODELING
In many cases, it is not appropriate to describe a module structurally. One such case is a module which is at the bottom of the hierarchy of some other structural description
For example, if you are designing a system using IC packages bought from an IC shop, you do not need to describe the internal structure of an IC. In such cases, a description of the function performed by the module is required, without reference to its actual internal structure. Such a description is called a functional or behavioral description.
For example, if you are designing a system using IC packages bought from an IC shop, you do not need to describe the internal structure of an IC. In such cases, a description of the function performed by the module is required, without reference to its actual internal structure. Such a description is called a functional or behavioral description.
To illustrate this , suppose that the function of the entity F is the exclusive or function, then a behavioral description of F could be the Boolean function Y = A.B+A.B
More complex behaviors cannot be described purely as function of inputs. In systems with feedback, the outputs are also a function of time. VHDL solves this problem by allowing description of behavior in the form of an executable program.
7.10 MIXED STYLE OF MODELING
Here the above three modeling styles are mixed in a single architecture body, we could use the component instantiation statements (that represents a structure),concurrent signal assignment statement(that represent data flow)and process statements(that represent behavior).
7.11 CONFIGURATION DECLARATION
A component declared can be thought of as` template for a design entity. The binding of an entity to this template is achieved through a configuration declaration. This declaration can also be used to specify actual generic constants for components and blocks. So the configuration declaration plays a pivotal role in organizing a design description in preparation for simulation or other processing.
7.12 PACKAGE AND PACKAGE BODY DECLARATION
A package is a collection of types, constants, subprograms and possibly other things, usually intended to implement some particular service or to isolate a group of related items. In particular, the details of constant values and subprogram bodies can be hidden from user of a package, with only their interfaces made visible. A package may be split into two parts: a package declaration, which defines its interface, and a package body, which defines the deferred details. The body part may be omitted if there are no deferred details.
8. TOOL USED
8.1 Mentor Graphics ModelSim
Introduction
ModelSim 6.5f is a verification and simulation tool for VHDL, Verilog, System Verilog, SystemC, and mixed-language designs.
Basic Simulation Flow
The following diagram shows the basic steps for simulating a design in ModelSim.
• Creating the Working Library
In ModelSim, all designs are compiled into a library. You typically start a new simulation in ModelSim by creating a working library called "work," which is the default library name used by the compiler as the default destination for compiled design units.
• Compiling Your Design
After creating the working library, you compile your design units into it. The ModelSim library format is compatible across all supported platforms. You can simulate your design on any platform without having to recompile your design.
• Loading the Simulator with Your Design and Running the Simulation
With the design compiled, you load the simulator with your design by invoking the simulator on a top-level module (Verilog) or a configuration or entity/architecture pair (VHDL). Assuming the design loads successfully, the simulation time is set to zero, and you enter a run command to begin simulation.
• Debugging Your Results
If you don’t get the results you expect, you can use ModelSim’s robust debugging environment to track down the cause of the problem.
Basic Simulation
In this we will go step-by-step through the basic simulation flow:
Create the Working Design Library
Before you can simulate a design, you must first create a library and compile the source code into that library.
1. Create a new directory and copy the design files into it.
Start by creating a new directory for this exercise (in case other users will be working with these lessons).
2. Start ModelSim if necessary.
a. Type vsim at a UNIX shell prompt or use the ModelSim icon in Windows. Upon opening ModelSim for the first time, you will see the Welcome to ModelSim dialog. Click Close.
b. Select File > Change Directory and change to the directory you created in step1.
3. Create the working library.
a. Select File > New > Library. This opens a dialog where you specify physical and logical names for the library (Figure 3-2). You can create a new library or map to an existing library. We’ll be doing the former.
b. Type work in the Library Name field (if it isn’t already entered automatically).
Basic Simulation
c. Click OK.
Create the Working Design Library
ModelSim creates a directory called work and writes a specially-formatted file named _info into that directory. The _info file must remain in the directory to distinguish it as a ModelSim library. Do not edit the folder contents from your operating system; all changes should be made from within ModelSim. ModelSim also adds the library to the Library window (Figure 3-3) and records the library mapping for future reference in the ModelSim initialization file (modelsim.ini).
Compile the Design
With the working library created, you are ready to compile your source files. You can compile by using the menus and dialogs of the graphic interface, as in the Verilog example below, or by entering a command at the ModelSim> prompt.
1. Compile counter.v and tcounter.v.
a. Select Compile > Compile. This opens the Compile Source Files dialog
(Figure 3-4). If the Compile menu option is not available, you probably have a project open. If so, close the project by making the Library window active and selecting File > Close from the menus.
b. Select both counter.v and tcounter.v modules from the Compile Source Files dialog and click compile. The files are compiled into the work library.
c. When compile is finished, click Done.
2. View the compiled design units.
a. In the Library window, click the ’+’ icon next to the work library and you will see two design units (Figure 3-5). You can also see their types (Modules, Entities, etc.) and the path to the underlying source files.
Load the Design
1. Load the test_counter module into the simulator.
a. Enter the following command at the ModelSim> prompt in the Transcript window: vsim -voptargs="+acc" test_counter Basic Simulation
To the right of the Structure (sim) window you will see an Objects window and a Processes window (Figure 3-7). The Objects window shows the names and current values of data objects in the current region selected in the Structure (sim) window. Data objects include signals, nets, registers, constants and variables not declared in a process, generics, parameters, and member data variables of a SystemC module. The Processes window displays a list of HDL and SystemC processes in one of four viewing modes: Active, In Region, Design, and Hierarchical. The Design view mode is intended for primary navigation of ESL (Electronic System Level) designs where processes are a foremost consideration. By default, this window displays the active processes in your simulation (Active view mode).
Run the Simulation
Now you will open the Wave window, add signals to it, then run the simulation.
1. Open the Wave window.
a. Enter view wave at the command line. The Wave window opens in the right side of the Main window. Resize it so it is visible. You can also use the View > Wave menu selection to open a Wave window. The Wave window is just one of several debugging windows available on the View menu.
2. Add signals to the Wave window.
a. In the Structure (sim) window, right-click test_counter to open a popup context
menu.
b. Select Add > To Wave > All items in region (Figure 3-8).
All signals in the design are added to the Wave window.
3. Run the simulation.
a. Click the Run icon. The simulation runs for 100 ns (the default simulation length) and waves are drawn in the Wave window.
b. Enter run 500 at the VSIM> prompt in the Transcript window. The simulation advances another 500 ns for a total of 600 ns (Figure 3-9).
c. Click the Run -All icon on the Main or Wave window toolbar.
The simulation continues running until you execute a break command or it
hits a statement in your code (e.g., a Verilog $stop statement) that halts the
simulation.
8.2 XlLlNX ISE PROJECT NAVIGATOR
Xilinx ISE (integrated software environment) controls all aspects of the development flow. Project Navigator is a graphical interface for users to access software tools and relevant files associated with the project. We use it to launch all development tasks except ModelSim simulation.
The default ISE window is divided into four sub windows:
• Sources window (top left): hierarchically displays the files included in the project
• Processes window (middle left): displays available processes for the source file currently selected
• Transcript window (bottom): displays status messages, errors, and warnings
• Workplace window (top right): contains multiple document windows (such as HDL code, report, schematic, and so on) for viewing and editing.
Each sub window may be resized, moved, docked, or undocked. The default layout can be restored by selecting View > Restore. Note that a sub window may contain multiple pages. The tabs at the bottom are used to select the desired page.
Sources window
The sources window is used mainly to display files associated with the current project. A typical source window, which corresponds to the design of Listing 2.2,is shown in Figure 2.6. The top drop-down list, labeled Sources for, specifies the current design view. The synthesis/implementation view should be selected since we use ISE only for synthesis and implementation. There are three tabs at the bottom, labeled Sources, Snapshots, and Libraries. The Sources tab displays the project name, the FPGA device specified, and user documents and design files. The modules are displayed according to the internal design hierarchy. In Figure 2.6, the eq2 and eql entities reflect the hierarchy of Listing 2.2. The eq2 module also includes the eq-s3. ucf file, which specifies the constraints of the design. We can open a file in the workplace window by double-clicking the corresponding module. A top-level module icon can be placed next to a module, as in the eq2 module, to invoke synthesis and implementation for this particular module. The Snapshots tab displays project’s “snapshots,” which are copies of previously stored project files. The Libraries tab shows all libraries associated with the project.
Processes window
The processes window displays the processes available. The display is context sensitive and the available processes are based on source type selected in the sources window. For example, the eq2 module, which is set as the top-level module, is selected in Figure 2.6. The available processes are displayed in the processes window, as shown in Figure 2.7, Some processes may also contain several sub processes. We can initiate a process by clicking on the corresponding icon. ISE incorporates the “auto make” technology, which automatically runs the processes necessary to get to the desired step. For example, when we initiate the Generate Programming File process, ISE automatically invokes the Synthesize and Implement Design processes since file generation is dependent on the implementation result, which, in turn, is dependent on the synthesis result.
Transcript window
The transcript window is used to display the progress of a process and relevant messages. The Console page displays errors, warnings, and information messages. An error is signified by a red X mark next to the message and a warning is signified by a yellow! mark. The Warnings and Errors pages display only warning and error messages.
Workplace window
The workplace window is for users to view and edit various types of files. We use it to perform two main tasks. The first task is to view and edit the HDL and constraint files. The default editor is the ISE Text Editor, which is a simple text editor with features to assist creation of the HDL code. The second task is to check the design summary and various reports.
Xilinx ISE consists of an array of software tools.
There are four major steps:
1. Create the design project and HDL codes.
2. Create a test bench and perform RTL simulation.
3. Add a constraint file and synthesize and implement the code.
4. Generate and download the configuration file to an FPGA device.
Create the design project and HDL codes
There are three tasks in this step:
• Create a project.
• Add or create HDL files.
• Check the HDL syntax.
Create a project
An ISE project contains basic information of a design, which includes
the source files and a target device. A new project can be created as follows:
1. Select Start > All Programs > Xilinx ISE >Project Navigator (or wherever ISE resides)to launch the ISE project navigator.
2. In Project Navigator, select File > New Project. The New Project Wizard – Create New project dialog appears. Enter the project name as eq2 and the location, and verify that HDL is selected in the Top-level Source Type field. Click Next.
3. The New Project Wizard - Device Properties dialog appears. We need to enter the desired target device in this dialog. This information can be found in FPGA board manual or by checking the marking on the top of the FPGA chip. For a typical S3 board, select the following:
• Product Category: All
• Family: Spartan3
• Device: XC3S200
• Package: FT256
• Speed: -4
• Synthesis Tool: XST (VHDL/Verilog)
We also need to verify that the Xilinx XST software is selected for synthesis. After a project is created, we can create or add the relevant HDL files and a constraint file.
4. Click Next a few times to go through the remaining dialogs and then click Finish to complete the creation.
Create a new HDL file
If a file does not exist, we must create a new source file. The procedure to create a new HDL file is:
1. Select Project >New Source. The New Source Wizard - Select Source Type dialog appears. Select VHDL Module and type the file name, eq2. Click Next.
2. The next dialog appears. This dialog allows us to enter port names. These names are then later embedded in the HDL code. Enter the 1/0 port information Click Next.
3. Click Finish and a new HDL text editor window appears in the workplace window. The software automatically generates the HDL skeleton, which includes a comment header, library clauses, an entity declaration, and an empty architecture body.
4. By default, ISE version 8.2 generates the following library clauses:
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
The two libraries are not IEEE standard and should be replaced with
use IEEE. NUMERIC_STD.ALL;
5. Use the editor to enter the HDL code and save the file.
6. Repeat the process to create another file for the code .
Add existing files
If a file already exists, it can be added to the project as follows:
1. Select Project >Add Source. A dialog window appears.
2. Go to the desired directory and select the desired files. Click Open and a new dialog appears
3. Click OK to complete the addition. These files now appear in the sources window of the project navigator.
Check the code syntax
After completing a new HDL file, we need to check the syntax of the code:
1. Select the desired file in the source window.
2. In the processes window, click the + icon next to Synthesize to expand the process hierarc
