Abstract
Low-density parity-check (LDPC) code, a very promising near-optimal error correction code (ECC), is being widely considered in next generation industry standards. The VLSI implementation of high-speed LDPC decoder remains a big challenge. This paper presents the construction of a new class of implementation-oriented LDPC codes, namely shift-LDPC codes. With girth optimization, this kind of codes can perform as well as computer generated random codes. More importantly, the decoder can be efficiently implemented to obtain very high decoding speeds. In addition, more than 50% of message memory can be generally saved over conventional partially parallel decoder architectures. We demonstrate the benefits of the proposed techniques with an application-specific integrated circuit (ASIC) design (in 0.18- m CMOS) for a 8192-bit regular LDPC code, which can achieve 5 Gb/s throughput at 15 iterations. Index Terms—Error correction codes (ECC), low-density parity-check (LDPC) codes, Min-Sum algorithm, parallel processing, VLSI.
I. INTRODUCTION
ERROR correction codes (ECC) are widely applied in modern digital communication systems. Turbo codes and low-density parity-check (LDPC) codes [1] are the two most popular ECC that have near the Shannon limit performance. Since the rediscovery of LDPC codes [2], significant improvements have been experienced on the design and analysis of LDPC codes. However, the realization of a high speed LDPC decoder implementation still remains a big challenge and is a crucial issue determining how well we can exploit the unmatched merits of the LDPC codes in practical applications. A satisfying LDPC decoder usually means: good error correction performance, low hardware complexity and high throughput. To implement the decoder directly in its inherent parallel manner may get the highest decoding throughput. But for large codeword lengths (e.g., larger than 1000 bits), to avoid routing conflict, the complex interconnection may take up more than half of the chip area [3]. Both serial and partly parallel VLSI architectures are well studied nowadays [4]–[8]. However, none of these approaches are good for very high throughput (i.e., multi-gigabits per second) applications. In this paper, we propose a new LDPC decoder architecture targeting for multi-gigabits per second applications. The architecture has three major merits. 1) Memory Efficient. By exploring the special features of the Min-Sum [9], [10] decoding algorithm, the proposed architecture can generally save over fifty percent of message memory over the conventional design for high rate codes. 2) Highly Parallel. The architecture can normally exploit more level of parallelism in the decoding algorithm than conventional partially parallel decoder architectures [4], [5]. 3) Low Routing Complexity. Through introducing a special structure in the parity check matrix, the complex message passing between variable nodes and check nodes can be alleviated by the regular communication between check nodes. The codes suited for this kind of decoder architecture are named shift-LDPC codes. The remainder of this paper is organized as follows. In Section II, a brief review of LDPC codes is given. In Section III, the shift LDPC code construction is discussed. The decoder architecture is presented in Section IV. In Section V, an application- specific integrated circuit (ASIC) implementation of an 8192-bit rate-7/8 LDPC code based on the proposed architecture is presented. Section VI gives experimental results and concludes this paper.


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