19-04-2011, 03:09 PM
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REGISTER ORGANIZATION OF 8086
8086 has a powerful set of registers containing general purpose registers and special purpose registers. All registers of 8086 are 16 bit registers. The general purpose registers can be used as either 8 bit register or 16 bit registers. The general purpose registers are either used for holding data, variables and intermediate results temporarily or for the purposes like a counter or for storing offset address for some particular addressing modes etc. The special purpose registers, pointers, index registers or as offset storage registers for particular addressing modes.
GENERAL PURPOSE REGISTERS
The register AX is the general purpose 16 bit accumulator, with the lower order 8-bits of AX designated as AL and higher as AH. AL can be used as an 8-bit accumulator for 8-bit operations. This is the most important general purpose register having multiple functions. The register BX is used as an offset storage for forming physical addresses in case of certain addressing modes. The register CX is used as a default counter in case of string and loop instructions. The register DX is a general purpose register which may be used as implicit operand or destination in case of a few instructions.
SEGMENT REGISTERS
Unlike the 8085, the 8086 addresses the segmented memory. The complete one mega byte memory, which the 8086 is able to address, is divided into 16 logical segments. Each segment thus contains 64kb of memory. There are four segment registers, viz. code
GENERAL PURPOSE REGISTER POINTERS AND SEGEMENT
INDEX REGISTER REGISTER
segment register (CS), Data segment register (DS), stack segment register (SS) and Extra segment (ES). The code segment register (CS) is used for addressing a memory location in the code segment of the memory, where the executable program is stored. The data segment register (DS) is used for addressing a memory location in the data segment, where data is stored. Similarly, the extra segment register (ES) is also used for addressing a memory location containing data. The stack segment is used for addressing the stack segment of the memory. The stack segment is that segmented of memory which is used to store stack data. The CPU uses stack for temporarily storing important data. While addressing any location in the memory bank, the physical address is calculated from two parts, the first is segment addresses, related to different segments. The advantage of this scheme is that instead of maintaining a 20-bit register for a physical address, the processor just maintains two 16-bit registers which are within the word length capacity of the machine. Thus the CS, DS, SS, ES segment registers contain the segment addresses for the code, data, stack and extra segments of the memory. All these segments are the logical segments. They may or may not be physically separated.
POINTERS AND INDEX REGISTERS
The pointer contains offset within the particular segment. The pointers IP, BP & SP, usually contain offsets within the code (IP) and stack (BP & SP) segments. The index registers are used as general purpose registers as well as for the offset storage in case of indexed, base indexed and relative based index addressing mode. The register SI is generally used to store the offset of source data or extra segment while the register DI is used to store the offset of destination in data or extra segment. The index registers are particularly useful for string manipulation.
FLAG REGISTER
The 8086 flag register contents indicate the results of computation in the ALU. It also contains some flag bits to control the CPU operation. 8086 has a 16-bit flag register. Details of the flag register are:
Overflow Flag (OF) - Set if the result is too large positive number, or is too small negative number to fit into destination operand. It is also set when there is a carry/borrow into the MSB but no carry/borrow is generated out of the MSB.
Direction Flag (DF) - If set then string manipulation instructions will auto-decrement index registers. If cleared then the index registers will be auto-incremented.
Interrupt-enable Flag (IF) – If set then it allows interruption of a program by interrupts. If cleared then it masks the interrupts.
Trap Flag (TF) - If set then single-step interrupt will occur after the next instruction.
Sign Flag (SF) - Set if the most significant bit of the result is set.
Zero Flag (ZF) - Set if the result is zero.
Auxiliary carry Flag (AF) - Set if there was a carry from or borrow to bits3 to bit4 in the AL register.
Parity Flag (PF) - Set if parity (the number of "1" bits) in the low-order byte of the result is even.
Carry Flag (CF) - Set if there was a carry from or borrow to the most significant bit during last result calculation.
ADDRESSING MODES
The different ways in which a processor can access data are referred to as its addressing modes. Depending upon the data types being used in the instruction and the memory addressing modes, any instruction may belong to one or more addressing modes. The various addressing modes of 8086 are:
1. Immediate: In this type of addressing, immediate data is a part of the instruction, and appears in the form of the successive byte or bytes. E.g. MOV AX, 0005H.
2. Direct: In this addressing mode, a 16-bit memory address (offset) is directly specified in the instruction as a part of it. E.g. MOV AX, [5000H]
3. Register: The data is stored in a register and it is referred using the particular register. All the registers, except IP, may be used in this mode.
Example MOV BX, AX.
4. Register Indirect: Here, the offset of data is either in BX or SI or DI registers. The default segment is either DS or ES. The data is supposed to be available at the address pointed to by the content of any of the above registers in default data segment.
E.g. MOV AX, [BX]
5. Indexed: In this addressing mode, the offset of the operand is stored in one of the index registers. DS is the default segments for index register SI. In case of string instructions, DS and ES are default segments for SI and DI respectively.
E.g. MOV AX,[SI]
6. Register Relative: In this addressing mode, the data is available at an effective address formed by adding an 8-bit or 16-bit displacement with the content of any of registers BX, BP, SI and DI in the default (either DS or ES segment) . E.g. MOV AX, 50H[BX]
7. Based Indexed: Here, the effective address of data is formed by adding content of a base register (BX or BP) to the content of an index register (SI or DI). The default segment register may be ES or DS. E.g. MOV AX,[BX][SI]
8. Relative Based Indexed: The effective address is formed by adding an 8 bit or 16-bit displacement with the sum of contents of any of the base registers (BX or BP) and any one of the index registers, in a default segment. E.g. MOV Ax, 50 H [BX][SI]
9. Intrasegment direct mode: In this mode, the address in which the control is to be transferred lies in the same segment in which the control transfer instruction lies and appears directly in the instruction as an immediate displacement value. The effective address to which the control will be transferred is given by the sum of 8-bit or 16-bit displacement an current control of IP. E.g. JMP NEAR PTR LABEL
10. Intrasegment Indirect Mode: In this mode, the displacement to which the control is to be transferred lies in the same segment in which the control transfer instruction lies but it is passed to the instruction indirectly. E.g. JMP [BX+5000H]
11. Intersegment Direct: In this mode, the address to which the control is to be transferred is in a different segment. This addressing mode provides a means of branching from one code segment to another. Here the CS and IP of the destination address are specified directly in the instruction. E.g. JMP 5000H:2000H
12. Intersegment Indirect: In this mode, the address to which the control is to be transferred lies in a different segment and is passed to the instruction indirectly, i.e. contents of a memory block containing four bytes, i.e. IP (LSB), IP (MSB), CS (LSB), CS (MSB) sequentially. E.g. JMP [2000H]
INSTRUCTION SET OF 8086/8088
Data Copy Transfer Instruction: This type of the instruction is used to transfer the data from source operand to the destination operand. All these store, move, load, exchange, input and output instructions belong to this category.
Arithmetic and Logical Instructions: All the instructions performing arithmetic and logical, increment and decrement, compare and scan instructions belong to this category.
Branch Instruction: These instructions transfer the control of execution to the specified address. All the call, jump, interrupt and the return instructions belong to this class.
Loop Instructions: If the instructions have REP prefix with CX used as a count register, they can be used to implement the conditional and unconditional loop. The LOOP, LOOPNZ, LOOPZ instruction belong to this category.
Machine Control Instruction: These instructions control the machine status. NOP, HLT, WAIT and LOCK instructions belong to this class.
Flag Manipulations Instruction: All the instructions which directly affect the flag registers, come under this group of instructions. Instructions like CLD, STD, CLI, STI, etc.
This kit is a single board microprocessor training kit configured around INTEL 16 bit, 8086. In this kit, the 8086 IC is replaceable by other processors like 8088 also.
Operating Modes: This kit is designed to operate in max mode (pin 33:-0=max mode, 1=min).
Minimum mode- when we need just one processor chip.
Maximum mode- for complex operations, we need to attach more processors.
