26-04-2011, 11:23 AM
PRESENTED BY
RAMYA SAHITYA .J
RAMYA .V
REVATHI .K
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AIM OF THE PROJECT
• This project deals with design of scramblers/ descramblers for use with SONET and OTN optical networks.
• Writing VHDL code for scrambler/ descrambler and performing synthesis and simulation on FPGA.
ABOUT FPGA
• FPGA
• FPGA SERIES
FAMILY NAME
DEVICE NAME
PACKAGE
SPEED
SCRAMBLING
• Used for sufficent
0-1 transitions
• Scrambler is 7 bit self-synchronizing
• Polynomial X7 + X6 + 1
• Scrambler is initialized with ones
SONET
• Bellcore 1985
• ITU-T Standard
• 2 sides of SONET
• 3 layers of SONET
Physical layer
Line layer
Path layer
Self healing rings(APS)
Span & ring switching
2F-UPSR, 2F/4F BLSR
DoS
GFP
VCAT
LCAS
OTN
• Manages optical signals in optical domain
• Long distance Tx
• Stronger FEC
• 3 layers
OTS
OTM
OCh