02-02-2015, 04:08 PM
i need vhdl/verilog implementation of 8 bit mac unit using wallce tree multiplier and reversible gates
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implementation of reversible multiplier verilog code
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i need vhdl/verilog implementation of 8 bit mac unit using wallce tree multiplier and reversible gates
20-03-2017, 11:54 AM
Multiplier circuits play an important role in reversible computing, which is useful in a number of areas, such as low power CMOS design, optical computing, DNA computing and bioinformatics. Here we propose a new reversible multiplier circuit with optimized hardware complexity. The optimized multiplier circuit is compared with the previous proposals. We have shown that the quantum cost of previous proposals can be further reduced with the aid of existing local optimization algorithms (eg template matching, mobile rule and elimination rule). A systematic protocol for quantum cost reduction has been proposed. It has also been shown that the advantage in the gate count obtained in some of the above proposals by the introduction of new reversible gates is an artefact and if allowed, then each block of circuit can be reduced to a single gate. In addition, it is shown that the 4x4 reversible floodgates proposed for designing a multiplier circuit component (full adder) are neither unique nor special and many such 4x4 gates can be proposed. As an example, three of these new gates have been presented and the proposed gates are shown to be universal. It also shows that the total cost of our design is minimal. Reversible logic gates are highly demanded by future computing technologies, as they are known to produce zero power dissipation under ideal conditions. A digital combinational logic circuit is reversible if it assigns each input pattern to a single output pattern. These circuits are of interest in quantum computing, optical computing, nanotechnology and low-power CMOS design. Low power consumption and smaller area are some of the most important criteria for high performance systems. Optimizing speed and multiplier area is a major design problem.
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