How to Use IIC Module on M68HC08, HCS08, and HCS12 MCUs

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Introduction
This application note is an example of how to use the IIC
module on Freescale’s MCUs. The IIC module can be
used in the master or slave mode, respectively. In this
case, the master mode communicates with the serial
EEPROM because the IIC bus is used mainly for
communication between an MCU and a IIC peripheral
device. The IIC bus can communicate directly between
two MCUs, but the SPI bus is better for this task.


IIC Bus Summary
The IIC bus is a bidirectional, two-wire bus based on the wired AND (open drain) connection between
master and slave devices. For proper functionality, pull-up resistors are used. Each transfer originates from
the master device and is acknowledged or answered by the slave device.


IIC Bus Terminology
The following IIC bus terminology is used in this application note:
• Transmitter — Device that sends data to the bus. A transmitter can put data on the bus of its own
accord (master transmitter), or respond to a request for data from another device (slave transmitter).
• Receiver — Device that receives data from the bus.
• Master — Component that initializes a transfer, generates the clock signal, and terminates the
transfer. A master can be a transmitter or a receiver.
• Slave — Device addressed by master. A slave can be a receiver or a transmitter.
• Multi-master — Ability for more than one master to co-exist on the bus without collision or data
loss.
• Arbitration — Prearranged procedure that authorizes only one master at a time to take control of
the bus.
• Synchronization — Prearranged procedure that synchronizes the clock signals provided by two
or more masters.
• SDA — Data signal line (Serial DAta).
• SCL — Clock signal line (Serial CLock).


Bus Communication
The bus transfer protocol is based on the byte transfers followed by an acknowledge bit (ACK). The byte
transfer starts with the most significant bit (MSB) to the least significant bit (LSB). The SCL positive clock
impulses clock each bit. The 9th SCL impulse clocks the ACK bit.
Every bus transfer originates from a master device which sends the START condition to the bus. The the
next consecutive bytes’ sequence depends on the data being transferred through the IIC bus.


Control Byte
The control byte always follows the START condition. The control byte selects and activates specific
devices on the bus; see Figure 3 for the control-byte structure. The first four bits represent the slave
device’s control code. For example, the control byte for the serial EEPROM is A0 (control code is ‘1010’
binary). The next three bits represent the chip selects of the connected EEPROMs on the bus. The
EEPROM uses these three bits for multiple device operations, but they are used as the higher bits of the
internal EEPROM address if the memory address byte is wider than 8 or 16 bits. This address depends on
the EEPROM capacity. For example, if the capacity is in the range of 16 kbits, these three bits represent
the highest three bits of the address.