04-05-2011, 12:52 PM
Abstract
The Fast Fourier Transform (FFT) is a computationally intensive digital signal processing (DSP) function widely used in applications such as imaging, software-defined radio, wireless communication, instrumentation. In this paper, a reconfigurable FFT design using Vedic multiplier with high speed and small area is presented. Urdhava Triyakbhyam algorithm of ancient Indian Vedic Mathematics is utilized to improve its efficiency. In the proposed architecture, the 4x4 bit multiplication operation is fragmented reconfigurable FFT modules. The 4x4 multiplication modules are implemented using small 2x2bit multipliers. Reconfigurability at run time is provided for attaining power saving. The reconfigurable FFT has been designed, optimized and implemented on an FPGA based system. This reconfigurable FFT is having the high speed and small area as compared to the conventional FFT.
1. INTRODUCTION
Digital signal processing (DSP) is the technology that is omnipresent in almost every engineering discipline. Faster additions and multiplications are of extreme importance in DSP for convolution, discrete Fourier transform, digital filters, etc. The core computing process is always a multiplication routine; therefore, DSP engineers are constantly looking for new algorithms and hardware to implement them. Vedic mathematics is the name given to the ancient system of mathematics, which was rediscovered, from the Vedas between 1911 and 1918 by Sri Bharati Krishna Tirthaji. The whole of Vedic mathematics is based on 16 sutras (word formulae) and manifests a unified structure of mathematics. As such, the methods are complementary, direct and easy.
Due to a growing demand for such complex DSP application, high speed, low cost system-on-a-chip (SOC) implementation of DSP algorithm are receiving increased the attention among the researchers and design engineer. Fast Fourier Transform (FFT) is the one of the fundamental operations that is typically performed in any DSP system. Basic formula of computation of FFT is
X (k) = WNnk 0 ≤ k ≤ N-1
The Fast Fourier Transform (FFT) is a computationally intensive digital signal processing (DSP) function widely used in applications such as imaging, software-defined radio, wireless communication, instrumentation and machine inspection. Historically, this has been a relatively difficult function to implement optimally in hardware leading many software designers to use digital signal processors in soft implementations.
Vedic Mathematics is the ancient system of mathematics which has a unique technique of calculations based on 16 Sutras. Employing these techniques in the computation algorithms of the coprocessor will reduce the complexity, execution time, area, power etc. In this paper reconfigurable FFT is proposed to design by Vedic mathematics. Urdhva tiryakbhyam, being a general multiplication formula, is equally applicable to all
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http://arxivpdf/1006.2811
