Design Considerations for High-Speed Low-Power Low-Voltage CMOS Analog-to-Digital Converters
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Introduction
The realization of signal sampling and quantization at high sample rates
with low power dissipation is an important goal in many applications, including
portable video devices such as camcorders, personal communication
devices such as wireless LAN transceivers, in the read channels of magnetic
storage devices using digital data detection, and many others. This paper
describes architecture and circuit approaches for the design of high-speed,
low-power pipeline analog-to-digital converters in CMOS


Techniques for CMOS Video-Rate A/D Conversion

Analog-to-digital conversion techniques can be categorized in many ways.
One convenient means of comparing techniques is to examine the number of
“analog clock cycles” required to produce one effective output sample of the
signal being quantized. Here an analog clock cycle usually involves analog
operations such as comparison, D/A converter settling, operational amplifier
settling, and so forth.


Operation at Lowered Power Supply Voltage
From a fundamental viewpoint, operation at reduced power supply voltages
is not advantageous from a power dissipation perspective for analog circuits
whose dynamic range is kT/C limited and whose power dissipation is
dominated by CV2 dynamic power in the capacitors storing analog state variables.
In this case in order to preserve dynamic range capacitor values must be
increased as the inverse square of the power supply voltage, precisely canceling
any advantage that would accrue in dynamic power.