[attachment=2568]


The file system must be user friendly as far as possible. Hence the operation on the system by tfie costumers must be limited. Thus the procedure for a search can be settled as follows. 'First of all the system displays a message "Search:-" to the costumer. The costumer must enter the first few letters of the name of the tram or the product or the patient. Then he must close the "enter" hey. Then the soft key 'FT' can be keyed to start the search. The system displays the details of if any match occurs. The "Tsc" %ey can 6e utilized to terminate the search mode.

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Presented By: Abhinand, A
Adarsh, R
Arif, M H
Bibindev, B P

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7i Keyboard
7i Display
Power Supply
(Block .diagram explanation
The main unit is the microcontroller, which is the master device and had ultimate control over the entire devices. JXlso it performs arithmetic and logical operations. Jftrwever it cannot store any data for permanently. This in needs another device, which can store the data and'soft ware and is caffed memory.
The data are enteredâ„¢ through the keyboard, fl PC/ATkeyboard'can be used in this section. 'Thus we can enter the alphanumeric characters to the system.
The ddta entered are alphanumeric fetters. Thus display unit must also display
the alphanumeric characters. .Hence we can use an intelligent LCD display having 2
\ fines. Or simply we can employ a 2x16 ^ne intelligent character COD
*
Circuit design
16X2 LINE CHiftACTER INTELLIGENT LCD
U'12 LCD
o or. o> < z o
T lii -
IO O C O < *
o4 tr« <r1 irt id
In this section we examine an intelligent Id display of one line, 16 characters per line that is interfaced to the programmable peripheral interface. These types of displays contain a liquid crystal display panel and an in built ucontroller. These are available in the market with various specifications such as 16x1 line, 20x2 lines, and 20x4 lines and with or without backlight. The displays with backlight will contain an additional panel of led which makes the reading even in dark. There are a number of choices for the color of the light.
The micro controller in the LCD display contains two internal byte ide registers, one for commands and the second for the characters to be displayed. The address of these registers can be selected with the help of the control pin 'RS' (pin 4). A logic high level on this pin will seled the register for the characters.
Pin I = Q<$pWD Pin 2= 14 = 5f
<Prn 3 = brigfitness. The brightness of the display mil be increased as the potential on this pin goes down.
(pin 4 = ^5 = register address; RS - 0 for command register
¢RS = 1 for character register. Tin 5 = <RfW, read or write control. <R/'W = 1 for read and-R/W = 0 for write Tin 6 = <E5V"; enable pin this pin must be at logic high level during the data
'Write operation. Tin 7-Tin 14 = T)irT)-Vin 15 aground Pin 16 =51'
The pins 15 e. 16 are optional and may not be in all displays. The commands are given below. In order to write a command the CR$ and the Rjidpins should be made low and the enable pin should be high. The 8-bit command can then he fed to the data lines.
0 0 0 0 0 0 0 1 clear CQD and memory
0 0 0 0 0 0 1 0 clear and home curser only
0 0 0 0 0 1 1/0 s screen action as display Character written
S = 1: shift screen S - 0; shift curser 1/0= /= tight I/O = 0 (eft
0 0 0 0 1 I) ( 8 D=I/0; S(RFF:\'0:\'OFF
C=1/0; ( CRSFROXOFF B = I/O;Curser bdnh/no blink,
0 0 0 1 S/C 0 0 S/(-I/O; Screen ¦( urser
K/F-l,0: shift otic (pace
Rj-
0 0 I DC V F 0 0 DC= I/O; S/4bits per char.
¦\=1/Q: 2 1 rou if char. (For 20x2 lines display ¦1=1/0; 5xJ0 Sc~ dots per character
The ASCII characters can he displayed by giving the ASCII data for the required character to the data lines. The R$ and the 'EiYpins should he at high level and the ¦R/'W line should Be toggled to low during the character write operation. The ASCII character for the capital letters 'A-~.' are '4F.H-5A Ifrespectively. The data '61 ://- 7 J If represents the lower case letters while the data M)h to 39fi represents the decimal numbers.
'Keyboard
The I'B'M keyboard can be a cheap alternative to a keyboard on a Micro controller development system. The diagram below shcru's the Scan Code assigned to the individual keys. The Scan code is shown on the bottom of the key. 'E.g. The Scan Code
for'ESC is 76. Jill the scan codes are shown in Keoc.
/~FT 05
06
04
oc
i^l(~&\ (J&)fi7)(H
36
j*Ej liEJ L66
Caps 58
( Q (J5j
1C
(jDJ I 24 J
r
1B
U
r
l3BJ(42
lHJ li2J I 54 J I, 5B.J
«J 5A
Shift
12
22J UlJ V
32
31
3A
4A
Shffi 59
Ctrl
11
SPACE 29
Jliill
1 E014 1
J&zn Codes for the basic (PC/AT keyboard The scan code assignments are quite random. In many cases the easiest way to convert the scan code to ASCII would be to use a look-up table. <Befow are the scan codes for the extendedkeyboard‚¬1, Numeric keypad.
E012E07C Scr
ScrL] 7E
E11477E1F014F077
>ausg Brit
Ins E070
'EeT E071
Num
77,
7
6C
6B
69
0
70
/
8
75
5
73
T 72
EC4A
The scan codes tell the 'Keyboard(Bios, what heys have pressed or released Take for example the 'JA' %ey. The 'A' §gy has a scan code of IQ (hex). When you press the %' hey, the keyboard will send 1C (drum its serial line. If we are still holding it down, for longer than it's type ma tic delay, another 1C will he sent. This keeps occurring until another hey has been pressed, or if the '/A' hey has been released. The keyboard only has one code for each hey. It doesn't care it the shift- hey has been pressed. It will still send the same code. It's up to tfie keyboard (BIOS to determine this and tale the appropriate action.
The (PC's JAT 'Keyboard is connected to external equipment using four wires. These wires are shown below for the 5 Tin <D/5V cMale (Plug <&<PS/2 (Plug.
5 (Pin <DI9f
l:KSBVCloci 2.K<B<D <Data 3.%/C
5. '+n''(T'CC) (PS/2
i.%m> cloci. ¦ 2.qsm>
S.'KBO Data 4.%/C
5.+TCCCCCJ 6.W/C
_/ /i/i// -wire can sometimes be found. This was once upon a time implemented as a "Keyboard T(§set, but today is left disconnected on JIT Keyboards. Both the KBD ClockandKfB'D 'Data are Open Collector bi-directionaf I/O Lines. If desired the Host can talk to the keyboard" using these Cities.
'Most keyboards arc specified to drain a maximum 3(X)mJ1. This will need to be considered when powering your devices.
The keyboard is free to send data to the host when both Tie K-BlJ Data and KM) ("Cock fines are high (Idle). The 'Kl&D (fockfuie can be used a* a (fear to send'fine. If the host takes the KBD (lockfine low, the keyboard'wiffbuff any data nut it'the K'BD (Cock is released, ic goes high. Should the Host take the K-B-D Data line fan and' then the keyboard will prepare to accept a command from the host.
'The transmission of data in the forward' direction, ie Keyboard to tiosi is d
one
with a frame of 11 hits. The first bit is a Start <Sit (Logic 0) followed by 8 data bits (LSB 'First}, one Parity 'Bit (Odd Parity) and a Stop 'Bit (Logic 1). 'Each Bit should be read on the Jailing edge of the clock.
Idle
Clock
Data
Idle
1
Start
t! f
dUUU
0 1 2!3 4 5 6!7!P
stop
-Keyboard \ -Hos!
The above waveform represents a one-byte transmission from the Keyboard', lite keyboard may not generally change it's data fine on the rising edge of the clock as shown
in the diagram. The data Cine only has to he valid on the failing edge of the cfoch^. 'The j
'Keyboard wiffgenerate the clocks The frequency of the cfoch.signaltypicahy ranges from 20 to 30 'KPhz. The Least Significant <Bit is always sent first.
(Power supply
'llie system requires a +5v suppfy. This can 6c delivered from the 2301 ¦' domestic suppfy. (Before applying this to the system we must step down this high voltage to an appropriate value. After thai it should he rectified. This will provide a unidirectional current. To achieve a +S'l''DC we should regulate this. All these are done in the pmver supply circuitry, which is explained Below.
A 12-0-12'V step down transformer is connected to provide the necessary! fan voltage. The transformer also worhj as an isolator Between the hot and cold end. The hot end refers to the 2301' supply, which is a hazardous one, and the cold one refers to the lenv, safe voltage. Now tin: hot portion appears only at the primary of the transformer. The secondary of the transformer deliver 121' ac pulses along with a ground.
This ac supply goes to a center tap rectifier, which converts the ac into a unidirectional voltage. The ripples in the resulting supply is filtered and smoothed By a
2200fJcF(D/251' capacitor. The 0.1/0F capacitor Bypasses any high frequency noises. The resulting supply has the magnitude aBove 17%'. This voltage is fed to the regulator 1Q 7805. This IC provides a regulated 3'1positive supply at its 3'* pin. The required input
i
\
\ I
for this is more than 7.5V. Also there is an LfET) in series with a M Q resistor. This will act as a power ON indicator.
'Microcontroller
31
19
18
RESET
EA/VPP
X1
X2
U2
PO.O(ADO P0.1(AD1 P0.2(AD2 P0.3(AD3 P0.4(AD4 P0.5(AD5 P0.6(AD6 P0.7(AD7 P1.0(T2 P1.1(T2EX P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0(A8) P2.1(A9) P2.2(A10) P2.3(A11) P2.4(A12) P2.5(A13) P2.6(A14) P2.7(A15) P3.0(RXD) P3.1COD) P3.2(INT0) P3.3(INT1) P3.4(T0) P3.5XQ) P3.6(WR) P3.7(RD)
39
38
37
36
35
34
33
32
PSEN
ALE/PRC-G
29
30
80C52
The 8-hit microcontroller 89Q52 from j\cTcMcEL is selected to control the system. Tim is a 40-pin chip, which contains four input /output ports, 256 hit ram, ,\h h\te of
prom. The power is applied across tfie 'Vcc (pin 40) and Cjnd(pin 20) pins. The externaf execution is eliminatedhy connecting the EJA pin to Vcc through a resistor.
Clockjnputs
The Xl and X2 inputs are connected to the ends of a piezo electric crystal TU'e can choose the crystal frequency from TMlu, to 24cMhz. )A(so both oj the crystal inputs are connected to ground through capacitors of vale 33pf. The clocl^pin connection are shown below.
P2 3(A11) P2 4(A12) P2.5(A13) P2 6<A14) P2.7(A15) P3.0(RXD) P3.KTXD) P3.2(INT0) P3 3<INT1) P3.4(T0) P3.5CT1) P3.6(WR) P3.7(RD)
25
26 27
28
10
11
12
13
14
15
16
17
(Rfset inputs
The figure shows the connections of the reset pin. The reset pin power On reset circuit. The capacitor voltage at the time of power on « id reset microcontroller. The voltage drops to zero shortly after seme time the reset condition and the microcontroller will start fetching now. <Ports
(Port
(D7 m (D5 <D4 <D3 <D1 TV of tfit p-rt
<P0 - \:jy
A 7 M JL5 A 4 JU 1 ,7 ¦!
11 . Iddntsi
Led
<B1 <D7/ Led Led Led Led led L.C-d
OE ‚¬>6" T>5 TJ4 ¦1)3 01 J.-'1 ' v Output
rom
¦ ¦
07 ¢D6 05 <D4 >m ./) / m Hi KM 1) TI ¦ ¦BI \$
<P3 ¢7 /,' nil A10 A 9 ns MX lagiem,
! XOKZS.s
(Feb fabrication
The first step of assembling is to procure a printed" circuit Board'. The fabrication oflfie program counter plays a crucial rote in tfie electronic field. The success if a circuit is also depends on the -:p(JB. J4s far as the cost is concerned tlie more than 25% of the total cost us gone for the design and fabrication,
lie are using a micro conlriller-based system that handles high frequencies hi the high frequency circuit the data may easily be -violated in the. ->'(" H due to the physical parameters. That is the track capacitance and inductance can cause the cross talk m the buses. Jtfso unwanted noise can Be induced to supply rails and from there il can affa i the total response. 'Hence the PCB design has a major role in the system performance.
The board is designed using a personal computer. '7he layout is drawn using the software "fldoSe 'PageMaker 6.5" The layout is printed in a 'butler sheet' using a laser printer. The layout is transferred to the copper clad sheet using the screen print procedure. -First a negative screen of the layout is prepared' with the help of a professional screen printer. Then the copper clad sheet is kept under this screen. 1 he-screen printing ink is pored on the screen and brushed' through the top if the screen. The panted board is kept under shade for few hours tiff the ink Become dry.
The etching medium is prepared %vith the un-hydrous ferric chloride and water. 'The printed hoard is kept in this solution tiff the exposed copper dissolves m the solution fully. After that the hoard is taken out andrinsed'in flowing water under a tap. The inkas removed with the help of (HC thinner (available in the paint shops1. The hoard is coated with solder in order prevent oxidation.
Another screen, which contains component side layout, is prepared and Ike same is printed on the component side of the board. A paper epoxy laminate is used as the board. Both component and the track.layout of the peripheral -iX is gn ¦- n above
Software section
Vtiderstanding the operation atufprocedures
-Beforegetting into tfie software, toe tnust reserve some j{jT;Ai arca_ data, Thus we can caff the (HJt3i area, 'which is reserved to store the data as search Suffer. The {PJ4'M locations, which hold the name and other at or the products or the patients or the train, can he named as data bujfe, locations that hold the data to he disp fayed can be called as display buffer
The algorithm of the system can Be fisted as Jo flows.
1. Initialize the '-Registers of the microcontroller
2. (Display the title of the -Firm in the first line of the LQD
3. ^Display "Search:-" in the Second" line of the LQD
4. Call the keyboard routine and chect{.auy of the hey is closed', 'flat
the hey is cfosed
5. Compare the data from the keyboard'in order tofind out whether a
' or a fetter key is closed. 'Jump to 8 if a command button is closed.
. ~
I
$ search buffer.
I
; 7. Increment the address of the search bufjer and compare the add
I
I address of the search buffer. If the address is betoxv the fast addr
Otherwise display "(Buffer fulfill the first. ii;n -.-/ -:. lew second
¦ and jump to 1 or restart the program.
8. Analyze the command and execute the com >roo ¦ a. (Restart the program if the "Esc" hoy :h
B. (Delete the last data in the c;,-o.i:: .or ; h';c ' Q'iacic
Space" hey is closed,
c. increment (for '”y hey) or decremo- ' .1 the
current Buffer and rotate i he Jo. :L;\ o ¢aeul
or decrement on the Buffer add i\xo o .trior
subtract 1 Oh rlthe '/*'%." V
d Start searching if the '<F1' o
e. (Edit the tithe f the '<F3' key . I.
/ Enter (Data in the (DJItn ln< ffer f fr. 14'.
g. (dear the memory if the 'T5' key is eh ¢¢>;«.
'There are two main routines in this system. < ; r-i :ne data
Buffer and the other is to search the data. In order ' data buffer
one must close the hey ''F4'.
The first step to enter the data in the data Buffer 'on of the
Buffer. Each item must Be entered in a fresh page. :.- ¦ ..-/ Tie data
Buffer must Be 'OOli'. i.e. the data for the first item «;« u the location
'OlOOiT, and that of the second one must start from ¦ f and the
(DO'HiV arrows in the hey Board can Be utilized to <eir Cpe ration
must first select tfie data Suffer address. Tfter selecting the required mem 'Fatter' hey must he closed. The current address of the buffer will be aion i fine of the memory.
The cursergoes to the second line of the LCD after the 'enter' C ¦we can edit the name or the number. The keyed'data will be slurwit on til the LCD. The display will he shifted as soon as u e enter the data- in the procedure, the ,(Esc' key must be closed.
The second main routine is to search the name. Ihe key rl initialize this routine. The system set the starting address of the dai Then the data in the first location of the search buffer-willbe data in ihe data buffer. The buffer address -unfile incrementedaru be repeated if the compared data are same. The data in the data /;;.¢/'.¢ on the L(rD if all the search data are equal to the data in the buff ¢
If there is no match with the search data and ihe data in the order add-unff be incremented by one. This wilt select the next page i above search process will be repeated here also. If there is no match page, the display unff be loaded with data '%rn result'. The sy. seconds.
Store data ascii data for the typed key in the SEARCH buffer.
Update the buffer address
Update the buffer ad-J dress as per the key' closed.
Delete the data if the Backspace key is closed.
F5
Clear Memory

Confirm the memory clear and store OOh in entire ram area if con-firmed.
Otherwise resume the routine
No

Store data ascii data for
the typed key in the
SEARCH buffer.
Update the buffer
address

Update the buffer ad-| dress as per the key closed.
Delete lite data if the Backspace key is closed.
0
Store data ascii data for the typed key in the ti¬tle buffer.
Update the buffer address
Update the buffer ad-dress as pet the key closed.
Delete the data if the
Backspace key is closed.
F4
Enter data
DlspIay"Room Number'1 in the first line and data] buffer content In the! second line. Call KeyBoard routine
Store data ascii data for the typed key in the DATA buffer.
Update the buffer address
Update the data bufferl address as per the key| closed.
Delete the data if the Backspace key is closed.
F1 &F2
Search
Load the address coun-ter with the initial ad-dress of the data buffer
Compare the data in the SEARCH buffer with the data in the DATA buffer. Select next page of the DATA buffer if the compared data are different. Continue this till a macth occures. Display "No Result" in the first line of the LCD if there is no match occures and the address of the DATA buffer Rolls Over. Reset the program after a few seconds. If there is any match occurs , go to the next block.
Increment the SEARCH buffer address and compare the data with '5A\ which repesent the enter key and there by the last data. If the data is not '5A\ then incremnet the address of the data buffer and continue the search. If the data is '5A' , which means all the data are same, then display the content of the DATA buffer in the second row of the led. Use curser controle keys to read the entire data. Use "Enter" key for next search.
J~ v” "J" -'J--'-- -
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Software
XiWD <EQV (XB4'J{ ; %m>
we eqv mm
%lt> azqp 0500K ; %<m cxxnc. i&JUD&R.
OE <EQp $353! ; EE<l*i{CtM QE
'Wtiž EQV 963C
>%p EQV 953f ; OE
LCD EQV 903C ; LCD LIMES EM <E QV OBOJf <RS EQV a$2J(
iMOT'Sm: #5GJC ; S<P ="503f
; 9i&VosK,#oaB{
j " Mm;09Jf,#Smf ; WKMK, = 00SOSWQfllMg A<M>RSS &T
J WE WIDE
MALL WBf ; DIS<PLAYTTTOE
'MO'V <lxHlJi,, #'MSCj8
ACALL %02 ; DIS<PL.AT'HSEA\R(31: 'TOSECOND LINE
I
j MC30. AC ALL A'iE'T ;ACJlLC%&t
j C3ME <R4, # 7(EJf,S-KCT
| SfMl'SE^Kltf
\ MfA: iH03'mp3R4 ; STOKE'DMA
t lM0'V'A,:K4
A CALL <DSP ; 331S<PALY'KWY
mew
I CJ'ME m #167CSRPC
| STMVSTA<RT
j SEA^CJC ; ^Q'VTIME TOAMAL'tSE WE'YQOA-QfP DATA
MO'Vm#lWC ; W^STXKTly^jAiDiy^ ¢MOVA, mp ; JCC = :FI<R$T(DATA 'FHPM SEA^RCAf<M)F<FE<R, 0NEA.#7EWJIXS All'MTOOOOIf
AXS: ; COM<PA<R£S THEE <BV<Fm^mWfWm ACCESS COTXE
CAME A, #2A3C.SWPATA ; COMPARES DATA WITH' *
iworp
owe m #3if,fam ; commws miA u ;ft
iwcskq
OWE m#3ZJC,3CiXM<E ; COMA:RFS 'DATA Wl'TJl
IWORQ
OWE m #33'K;HO!ME ; CO'MA^ES (DMA WlTM
<MCfl;(D<FI%#MSgi
MALL 'R01 ; (FRIWT-BDPTOW RQ1
MO-V083C,#01:}[
'MOV 0911, #007/" ; <%Eg 083fAWD 097/ = <EWE^Â¥Ptr.
CO'M ACALL'KfEY
OWE R5, #00tCCOM ; fU'MP J'F WO 'KlE Y'l.s i /.,
'MOI-'AeRJ
OWE A. #2C0iAi>W
S'fMPEXE
WW: ACALL (DS<P ; (DISPLAY CLOSED 'K&Y
ACALL ; STO-m (DATA FX2864
ACALL <DSA(D ; <DSlP A<DROf 2864
s:mecocM
<EM: OWE <R5, #W%EX1
ACALL (Dm. ; 'ESC KEY CLOSED
'EXE OWE <£->.. # 11-K;EX2 ACALL DEL
mi
<EX2: OWE (R5, #02Jf:FX3 ACALL <Pg£>7 'RfET
<EX3: OWE <R5, #03'K,(EX4 ACALL <pg<R7 (RF/F
<EX4: OWE <KS, #04'lf<FX5 ACALL <pgV(p (RFXF
<EX5: OWE <K5,#05CJ{,(EX6 MALL T^-DW
mr
<EX6: OWE <R5, # 12T0EX7 ; <F1 COEJFR^MEMORiY AJMFMCLR^
EX7:
ACALL ODOR, OWE <RJ, # FVJfAXS AJMTEVFT
; <F2 /)/'7 'HALE
<EX8: OWE «5. #14W;jfOiME ;<F3 EWT'ER/DTTA AJ-MF-DAV'i
FmiT: MO(' D'JT'R, #CMS$8
ACALL Msg
MOV 08W,#0OH MOV'09W,#5OJC MW8$SS
47/1X10: ACALL KEY MOT'AFRJ S'UmA> #204f 3CEXE ACALL nHiiR. ACALL vsn IWC09W
OWE Q9,x,#6(Yj{,<Eqyro
LJ'MFJfO'M'E
; 0809 = 005OK, TITLE <B'VFFE^
(DATA: iMOV'A,08'Jf ATFD A, #01JC
MO'VOSWA TXDTl: MOV 09K #00/1
iwcm'Ai^mwicjWBRomE^iymEss
; (BVTFFSRJTDDR.
<D&I0: ACALL -'KEY XIOVA/R4 STlXm A, #20K JCEXE ACALL liHCR
CREAT> FEY
; EXECUTE COMMA WD
; STORE DATA TO MEMORY
ACALL DS'PC ; V&DA'TE LCD
j 75VT 09/" ; MEXTLOCATIOM
COME 0M,#EE%EXLY[0
soMr-nvri
I (DEL: ; (DELETE
I (DEC &#{ ; (DfeCmMEftWEM L(
M 03;A, 0931
MOVcRj, it 203f
ACALL iVHAR, ; STORE 2i> i S : ME W
¢Â£1; (DEC 0931 ; (DECREMEMl M±:T j. Oi ¦RET
(PQRT: IMC 093f ; INCEWEMMET Mi :j JO ¦:
| <PgV(p: :MO3'A,#103f
| A(DD J\m3(
I MOV'093fJ
¦RET
I
svmA,#io3i
MOVQ93CA (RfET
MCL/R: ACALL (DL<R, MOV <DPmt #<MSCI2 ACALL (ROl
MOV(DPTR,#MS(J3 ; (DISVLA'Y CL}EA!RAlEM ACALL (R02
MCK3 ACALL 'K<E<Y : COMFItiM MEM CLE : R COME (R4, #003(, MOD S0M3PMCK.
MOD: C3ME <R5, #593f3fOME; <EXIT'<P^pM Ml "'
: MOV' 0&K, # 003 f
j MCri > 093% 0831 ; I'MITVA L MEM A DTML S
\
'MCV. MOV A, #0OK
MALL. 'WW% ; SftCWfE 00 TO 'MEM ACALL <DSA<D ; DISPLAY'MEMA'Vm$SSS MOVA-OSUf
C/WEA,#2(rfCMCl
MOi;E*H%#MSg4 ^DISPLAY iMEMMO'RYCLEAM-T)' ACALL KQ1 ACALL DLY L;JMP3fOME
SRPATA: MOV 083f, POEM'
MM> mi: #omi' ; sTA^riNg ATFDIIESS OE MEM =010031
\RE9EA3E MM ¦' HQ. # 103C; SlA^Xg A&&g$SS OE SEA Hi 3 C &C IiER=IQff
NXTT). VI. I: A(ALL WRO : READV EE! EROM MTM.ORY MOV'RJ, @R0 , MOVE (DATA IN MEMORY TO 4(1 CINE A ¢ RJXX'IPC : NEXT PA 9'E i E 'NO PA t,E
INC mi : INCRiEMENT MEM.OR- Y.A(DDRIisS
INC RO ; INCR(EME:NTSEARC3f(BV!PFE(RA'DDR:lSS
'MQVA^W
ONE. A,#7E3f,NXTDATA; (REPEAT SEAWSiEE CV^R^NT-DATA IS NOT
;TffE LAST ONE
MOV0931, #0031 : CLEAR..LOW O^QXRATTDRrESS ACALLiDSPC ; DISPLAYCU4^E,m4jATA
STAY ACALL SET
ONE <RJ, #003fSTAT ; J'l'MP IE NO 'KEY IS CLOSED MOV'A,R4
CANE A. #2G3fM>RIT ;EXECVTE COMMANDS S'JMPEXE
ONE A, # 7EJf,STAX ; SEAWAfATjAIN IT ENTE4(:KEX( L0SE4) SjMP'RESEAN
XXTP$: INC 083f : INORtEMEm3fICi3l<E(RA4XD-R:ESS
MOVA,083f
CJWL M, #2&K QfESEAM ; $E TRCJf 1Q -1 1: V /¢/ ; \ AT)(D<RESS IS
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After assembling, tfie micro controfferis programmed as p is powered without ICs. Tien tfie -voltages at different supph ncd circuit is switched OPK Then the chivs are inserted m their re:,-oe\ :a<.
i
circuit is energized. The working of the system can be explained ,
The transformer steps down the domestic supply to i I { - o unit rectifies this AC and'provides +5'l' regit fated supply. Tin circuits is already explained. [Now the CPU gets the supply reset due to the action of the power on reset circuit. Tin: reset the micro controller appears after some time determined by tin circuit.
The system enters in the search, mode. The data in the Jiep the LCD. The first row of the LQD is loaded-mill the name cr row the data "Search:-:'' is displayed. :Nbw the system califs ' The program will return to the main subroutine if and only if ate 'The keyboard subroutine places the ASCII data for the closed r system reloads the ASCI f data from this location to the act arm: (an¬il with 20li in order detect the type of the key, ie. whether the , key or a diameter key.
The system jumps to the fahef exe' if any of the command keys is dosed. Otherwise the ASCII data of the closed key is stored in the display buffer and the COD is refreshed. The content of the register is compared with 30h in order to detect, the fast locations of the display buffer. It is to be remembered that the user must close the 'Enter" key before the search routine is called.
The program jumps the fahef e.ye, if any of the assignedcommandCmlions are closed The ASCI I data is compared with different assigned mines and the program mil be diverted to the corresponding locations using jump instructions. The address locations are altered if the curser controlkeys are closed'. If main subroutines are called if any of the soft keys are closed
The user must closed the enter key in order to start the search, function. Since this system is supposed to operated'by the public, utmost care must be taken to presene the data in the memory. Hence all functions of the system, e.\cept search; are protected with authorization code. In our system. *J23 is given as the authorization code. The system compares the first data in the search buffer with 2Ah, the ASCII code of the *. A match will drive the program to edit mode. The rest of the codes are also confirmed. Any mismatch will reset the system, if the first data is not 2j4.fi, the system starts searching.
Tfie system loads the starting address 'OlOOh' in the registers OS and 09 h The register <Rf,) willbe loaded with the address of the search buffer. The data in the memory is moved to the accumulator and compare with data in the search buffer. The system increments the address of both data buffer and search buffer if there is a match. Then the data stored in the search buffer is compared'with '7<Eh in order to find out the fast data. 'The program repeats the above routine tiff aff of the data before the FEk are compared with the data in the data buffet: -'The system displays the details about the item in the data buffer on the LQT>. 'The user can scroll the details using the arrow keys. The enter hey itself can be used for nesct. match, The system will restart the search function will current address.
If the data in both buffers are different, the system increments the higher order address and clears the low order address. Then the content of the register OSh. higher order address, will be compared'with number 20h, in order to find out the fast location. The fast address of the <E<E<l^QiM 2864 is ITFTli Hence the address aScve this valise willresult in sovfi over. If the fast address occurs, the LQD will be loaded with ':.\o (Result'. 'The system calls a delay subroutine and resets afier the d'efay.
t row
The
In edit mode, LOO will display ''Edit' in the first fine. -The user can use the soft fays TT to T4. The system jumps to the 'Edit title subroutine if the ley (F2 is closed Tlere the authorities can enter the name or title, which is to be displayed on the first of the COO. The displays "'Edit title" on the first row and call the keyboard routine. \ letters that are keyed wiff be displayed on the screen of the COO- The subroutine will be terminated if the "'Esc" key u cfosed.
The details about the item can he edited' after cfadna the he: >}. ¢ 7 .;.
location of the data buffer is selected first using the arrow i(eys. 71',:
the selected item wifl be displayed on the screen ylft.ee select'-. j
number, the user can use the "Enter" hey. After closing the "-Lute.-' he j
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enter the name or the title. CXow we can edit the data, Any comma'
t his subroutine.
The program sends the confirm message "idea! display as soon as the hey (F1 is closed In order to dear the > hyy "')'. Otherwise the program will restart. Tie system ston memory locations. The memory locations will he increce-:
address is compared with 2Q(L The comparison is supposed \
jAfter clearing the memory, the system *«'/give us the messa.-n system reboots after the user acknowledges the routine through hi.
Features
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8* Byte* of ln^y»^ t^0^mmabi« nasi* Memory
Endurance: 1,6b0 Write/Erase Cydes
FuHy Static Operation; 0 Hz to 2* MHz
Three-level Program Memory Lock
256 x. 8-Bil Internal RAM
32 Programmable fO Lines
three 16-blt IlmeWCountem
E»B fi't interrupt Sources
Programmable Serial Channel
Low Power idle and Power Down Modes
Description
The AT89C52 is a low^power, highiperfurmance CMOS S^bil microcomputer with 8K bytes of Flash prograrrtrha&le and erasable read only rfiembry (PEROM) The device is manufactured using Atmei's high density nonvolatile memory technology and is compatible with Iheiodustfy Standard 80C51 artd 8GC52 aisuuCiiuii 6«i emu pmuui. I he on-crup flash allows the program memory to be raprogrammed in-system or Dy a conventional nonvolatile memory programmer. BV combining a versatile 8-bit CPU
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Block Diagram
P0.0- P0.7
P20
P2 7
tt f t
t t t
PORT 0 DRIVERS
PORT 2 DRIVERS
GND
rr
RAM ADDR REGISTER
RAM
PORT 0 LATCH
PORT 2 LATCH
QUICK FLASH
1
_
. B
REGISTER
ACC
STACK POINTER
PROGRAM ADDRESS REGISTER
TMP2
TMP1
ALU
PC
INCREMENTED
INTERRUPT, SERIAL PORT AND TIMER BLOCKS
PSW
PROGRAM COUNTER
PSES ¦+ ALE/PROG <-EA / Vw ” RST ”
TIMING AND CONTROL
INSTRUCTION REGISTER
PORT 1 LATCH
PORT 3 LATCH
OSC
PORT 1 DRIVERS
PORT 3 DRIVERS
H-H-H-H--M-t--H--l-!-t-
P1.0 - P1.7
P3.0 - P37
The AT89C52 provides the following standard features: 8K bytes of Flash, 256 bytes of RAM, 32 I/O lines, three 16-bit timer/counters, a six-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and dock cir¬cuitry. In addition, the AT89C52 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power Down Mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next hardware reset
Pin Description
Supply voltage.
GND
Ground.
PortO
Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs.
Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses to external pro¬gram and data memory. In this mode, PO has internal pullups.
Port 0 also receives the code bytes during Flash program¬ming and outputs the code bytes during program verification. External pullups are required during program verification.
Port 1
Port 1 is an 8-bit bidirectional I/O port with internal pullups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (l^) because of the internal pullups.
In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively, as shown in the following table.
Port 1 also receives the low-order address bytes during Flash programming and verification.
Port Pin Alternate Functions
P1 0 T2 (external count input to Timer/Counter 2), clock-out
P1.1 T2EX (Timer/Counter 2 capture/reload trigger and direction control)
Port 2
Port 2 is an 8-bit bidirectional I/O port with internal pullups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (!ž_) because of the internal puilups.
Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this application, Port 2 uses strong internal pul¬lups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ Rl), Port 2 emits the contents of the P2 Special Function Register.
Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.
Port 3
Port 3 is an 8-bit bidirectional I/O port with internal pullups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low wili source current (l(L) because of the pullups.
Port 3 also serves the functions of various special features of the AT89C51, as shown in the following table.
Port 3 also receives some control signals for Flash pro-gramming and verification.
Port Pin Alternate Functions
P3.0 RXD (serial input port)
P3.1 TXD (serial output port)
P3.2 INTO (external interrupt 0)
P3.3 INT1 (external interrupt 1)
P3.4 TO (timer 0 external input)
P3.5 T1 (timer 1 external input)
P3.6 WR (external data memory write strobe)
P3.7 RD (external data memory read strobe)
RST
Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device.
ALE/PROG
Address Latch Enable is an output pulse for latching the low byte of the address during accesses to external mem¬ory. This pin is also the program putee input (PROG) during Flash programming.
In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external tim¬ing or clocking purposes. Note, however, that one ALE
dm
pulse is skipped during each access to external data memory.
If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only dur¬ing a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect If the microcontroller is in external execution mode.
PSIN
Program Store Enable is the read strobe to external pro¬gram memory.
When the AT89C52 is executing code from external pro¬gram memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.
EA/Vpp
External Access Enable. EA must be strapped to GMD in order to enable the device to fetch code from external pro¬gram memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset.
EA should be strapped to Vcc for internal program executions.
This pin also receives the 12-volt programming enable volt¬age (Vpp) during Flash programming when 12-volt programming is selected.
XTAL1
Input to Ihe inverting oscillator amplifier and input to the internal clock operating circuit
OFFH
0F7H
OEFH
0E7H
OOFH
0D7H
OCFH
0C7H
06FH
0B7H
OAFH
0A7H
9FH
97H
6FH
87H
Special Function Registers
A map of the on-chip memory area called the Special Func¬tion Register (SFR) space is shown in Table 1.
Note that not all of the addresses are occupied, and unoc¬cupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indetermi¬nate effect.
User software should not write 1s to these unlisted loca¬tions, since they may be used in future products to invoke new features. In that case, the reset or inactive values of the new bits will always be 0.
Timer 2 Registers Control and status bits are contained in
registers T2CON (shown in Table 2) and T2MOD (shown in Table 4) for Timer 2. The register pair (RCAP2H, RCAP2L) are the Capture/Reload registers for Timer 2 in 16-bit cap¬ture mode or 16~bit auto-reload mode.
Interrupt Registers The individual interrupt enable bits are in the IE register. Two priorities can be set for each of the six interrupt sources in the IP register.
Table 2. T2CON”Timer/Counter 2 Control Register
Reset Value = 0000 0OO0B
T2CON Address = 0C8H Bit Addressable
Bit TF2 EXF2 RCLK TCLK EXEN2 | TR2 C/T2 CP/RL2
7 6 5 4 3 2 1 0
Symbol Function
TF2 Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software TF2 will not be set when either RCLK = 1 or TCLK = 1
EXF2 Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 ~ 1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be cteared by software. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1).
RCLK Receive dock enable. When set, causes the serial port to use Timer 2 overflow pulses for its receive dock in serial port Modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive dock.
TCLK Transmit dock enable. When set, causes the serial port to use Timer 2 overflow pulses for its transmft dock in serial port Modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit dock.
EXEN2 Timer 2 external enable. When set, allows a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX.
,-” ¦¦ TR2 Start/Stop control for Timer 2. TR2 = 1 starts the timer.
cm Timer or counter select for Timer 2. C/T2 = 0 for timer fundion. C/T2 = 1 for external event counter (falling edge triggered).
- CP/RT3 Capture/Reload select. CP/RL2 = 1 causes captures to occur on negative transitions at T2EX rf EXEN2 = 1. CP/RT3 " 0 causes automatic reloads to occur when Timer 2 overflows or negative transitions occur at T2EX when EXEN2 - 1. When either RCLK or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow.
Data Memory
The AT89C52 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a parallel address space to the Special Function Registers. That means the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space.
When an instruction accesses an internal location above address 7FH, the address mode used in the instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR space. Instructions that use direct addressing access SFR space.
For example, the following direct addressing instruction accesses the SFR at location 0A0H (which is P2).
MOV 0A0H, tfdata
Instructions that use indirect addressing access the upper 128 bytes of RAM. For example, the following indirect addressing instruction, where RO contains 0A0H, accesses the data byte at address 0A0H, rather thanT^ (whose address is 0A0H).
MOV 31!C, ftOsfta
Note that stack operations are examples of indirect addressing, so the upper 128 bytes of data RAM are avail¬able as stack space
iilrniT
Timer 0 and 1
Timer 0 and Timer 1 in the AT89C52 operate the same way as Timer 0 and Timer 1 in the AT89C51.
Timer 2
Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. The type of operation is selected by bit C/T2 in the SFR T2CON (shown in Table 2). Timer 2 has three operating modes: capture, auto-reload (up or down counting), and baud rate generator. The modes are selected by bits in T2CON, as shown in Table 3.
Timer 2 consists of two 8-bit registers, TH2 and TL2. In the Timer function, the TL2 register is incremented every machine cycle. Since a machine cycle consists of 12 oscil¬lator periods, the count rate is 1/12 of the oscillator frequency.
Table 3. Timer 2 Operating Modes
RCLK +TCLK CP/RL2 TR2 MODE
0 0 1 16-bit Auto-Reload
0 1 1 16-bit Capture
1 X 1 Baud Rate Generator
X X 0 (Off)
In the Counter function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, T2. In this function, the external input is sampled during S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since two machine cycles (24 oscillator periods) are required to recognize a 1-to-0 transi¬tion, the maximum count rate is 1/24 of the oscillator frequency. To ensure that a given level is sampled at least once before it changes, the level should be held for at least one full machine cycle.
Capture Mode
In the capture mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a 16-bit timer or counter which upon overflow sets bit TF2 in T2CON. This bit can then be used to generate an interrupt. If EXEN2 = 1, Timer 2 performs the same operation, but a 11-to-0 transition at external input T2EX also causes the cur¬rent value in TH2 and TL2 to be captured into RCAP2H and RCAP2L, respectively. In addition, the transition at T2EX causes bit EXF2 in T2CON to be set. The EXF2 bit, like TF2, can generate an interrupt. The capture mode is illusr trated in Figure 1.
Auto-reload (Up or Down Counter)
Timer 2 can be programmed to count up or down when configured in its 16-bit auto-reload mode. This feature is invoked by the DCEN (Down Counter Enable) bit located in the SFR T2MOD (see Table 4). Upon reset, the DCEN bit is set to 0 so that timer 2 will default to count up. When DCEN is set, Timer 2 can count up or down, depending on the value of the T2EX pin.
TF2
H
OVERFLOW
TIMER 2 INTERRUPT
(DOWN COUNTING RELOAD VALUE) OFFH
TOGGLE
>c
EXF2
OSC
-M2
OVERFLOW
C/T2 = 0
¢ TH2 TL2
TF2
T2 PIN
C/T2 = 1
CONTROL
TR2
A
COUNT DIRECTION 1 = UP 0=DOWN
TIMER 2 INTERRUPT
NOTE: OSC FREQ. IS DIVIDED BY 2. NOT 12
"0" "1"
A -
SMOD1
OSC
T2 PIN
C/T2 = 1
TRANSITION DETECTOR
CONTROL
TR2
TH2 TL2

RCAP2H RCAP2L
"1" "0"
RCLK Rx
+ 16 CLOCK

I
TCLK
Tx CLOCK
¦16
T2EX PINQ--
EXF2
TIMER 2 INTERRUPT
j CONTROL EXEN2
Figure 2 shows Timer 2 automatically counting up when DCEN = 0. In this mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 counts up to OFFFFH and then sets the TF2 bit upon overflow. The overflow also causes the timer registers to be reloaded with the 16-bit value in RCAP2H and RCAP2L. The values in Timer in Capture ModeRCAP2H and RCAP2L are preset by software. If EXEN2 = 1, a 16-bit reload can be triggered either by an overflow or by a 1-to-0 transition at external input T2EX. This transition also sets the EXF2 bit. Both the TF2 and EXF2 bits can generate an interrupt if enabled.
Setting the DCEN bit enables Timer 2 to count up or down, as shown in Figure 3. In this mode, the T2EX pin controls the direction of the count. A logic 1 at T2EX makes Timer 2 count up. The timer will overflow at OFFFFH and set the TF2 bit. This overflow also causes the 16-bit value in RCAP2H and RCAP2L to be reloaded into the timer regis¬ters, TH2 and TL2, respectively.
A logic 0 at T2EX makes Timer 2 count down. The timer underflows when TH2 and TL2 equal the values stored in RCAP2H and RCAP2L The underflow sets the TF2 bit and causes OFFFFH to be reloaded into the timer registers.
The EXF2 bit toggles whenever Timer 2 overflows or underflows and can be used as a 17th bit of resolution. In this operating mode, EXF2 does not flag an interrupt.
Figure 2. Timer 2 Auto Reload Mode (DCEN = 0)
OSC
+12

-cf O-
TH2 TL2
I CONTROL TR2
OVERFLOW
T2 PIN
C/T2 = 1
I
I I
RCAP2H RCAP2L
TIMER 2 INTERRUPT
T2EX PIN \~}
o-
EXF2
CONTROL
EXEN2
Table 4. T2MOD”Timer 2 Mode Control Register
Reset Value = XXXX XX00B
T2MOD Address = 0C9H Not Bit Addressable
” ” ” ” ” ” T20E DCEN
Bit 7 6 5 4 3 2 1 0
Symbol Function
” Not implemented, reserved for future
T20E Timer 2 Output Enable bit.
DCEN When set, this bit allows Timer 2 to be configured as an up/down counter.
Baud Rate Generator
Timer 2 is selected as the baud rate generator by setting TCLK and/or RCLK in T2CON (Table 2). Note that the baud rates for transmit and receive can be different if Timer 2 is used for the receiver or transmitter and Timer 1 is used for the other function. Setting RCLK and/or TCLK puts Timer 2 into its baud rate generator mode, as shown in Fig¬ure 4.
The baud rate generator mode is similar to the auto-reload mode, in that a rollover in TH2 causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2H and RCAP2L, which are preset by software.
Modes 1 and 3 Baud Rates =
The baud rates in Modes 1 and 3 are determined by Timer 2's overflow rate according to the following equation.
Timer 2 Overflow Rate 16
The Timer can be configured for either timer or counter operation. In most applications, it is configured for timer operation (CP/T2 = 0). The timer operation is different for Timer 2 when it is used as a baud rate generator. Normally, as a timer, it increments every machine cycle (at 1/12 the oscillator frequency). As a baud rate generator, however, it increments every state time (at 1/2 the oscillator fre¬quency). The baud rate formula is given below.
Baud Rate
Modes 1 and 3 _ Oscillator Frequency
32 x [65536 - (RCAP2H,RCAP2L)]
where (RCAP2H, RCAP2L) is the content of RCAP2H and RCAP2L taken as a 16-bit unsigned integer.
Timer 2 as a baud rate generator is shown in Figure 4. This figure is valid only if RCLK or TCLK = 1 in T2CON. Note that a rollover in TH2 does not set TF2 and will not gener¬ate an interrupt. Note too, that if EXEN2 is set, a 1-to-0 transition in T2EX will set EXF2 but will not cause a reload from (RCAP2H, RCAP2L) to (TH2, TL2). Thus when Timer 2 is in use as a baud rate generator, T2EX can be used at an extra external interrupt.
Note that when Timer 2 is running (TR2 = 1) as a timer in the baud rate generator mode, TH2 or TL2 should not be read from or written to. Under these conditions, the Timer is incremented every state time, and the results of a read or write may not be accurate. The RCAP2 registers may be read but should not be written to, because a write might overlap a reload and cause write and/or reload errors. The. timer should be turned off (clear TR2) before accessing thei Timer 2 or RCAP2 registers.
Figure 5. Timer 2 in Clock-out Mode
osc +2


O
TL2 TH2
(8-BITS) i (8-BITS)
TR2
i
RCAP2L RCAP2H
C/T2 BIT
P1.0 (T2)
3
2
o>x>-
P1.1 (T2EX)
O-
EXF2
TIMER 2 INTERRUPT
EXEN2
AMEl
9
Programmable Clock Out
A 50% duty cycle clock can be programmed to come out on P1.0, as shown in Figure 5. This pin, besides being a regu¬lar I/O pin, has two alternate functions. It can be programmed to input the external clock for Timer/Counter 2 or to output a 50% duty cycle clock ranging from 61 Hz to 4 MHz at a 16 MHz operating frequency.
To configure the Timer/Counter 2 as a clock generator, bit C/T2 (T2CON.1) must be cleared and bit T20E (T2MOD.1) must be set. Bit TR2 (T2CON.2) starts and stops the timer.
Clock-Out Frequency^
The clock-out frequency depends on the oscillator fre¬quency and the reload value of Timer 2 capture registers (RCAP2H, RCAP2L), as shown in the following equation.
Oscillator Fequency
4 x [65536 - (RCAP2H.RCAP2L)]
In the clock-out mode, Timer 2 roll-overs will not generate an interrupt. This behavior is similar to when Timer 2 is used as a baud-rate generator. It is possible to use Timer 2 as a baud-rate generator and a clock generator simulta¬neously. Note, however, that the baud-rate and clock-out frequencies cannot be determined independently from one another since they both use RCAP2H and RCAP2L.
UART
The UART in the AT89C52 operates the same way as the UART in the AT89C51.
Interrupts
The AT89C52 has a total of six interrupt vectors: two exter¬nal interrupts (INTO and I NT 1), three timer interrupts (Timers 0, 1, and 2), and the serial port interrupt. These interrupts are all shown in Figure 6.
Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all interrupts at once.
Note that Table 5 shows that bit position IE.6 is unimple-mented. In the AT89C51, bit position IE.5 is also unimplemented. User software should not write 1s to these bit positions, since they may be used in future AT89 products.
Timer 2 interrupt is generated by the logical OR of bits TF2 and EXF2 in register T2CON. Neither of these flags is cleared by hardware when the service routine is vectored to. In fact, the service routine may have to determine whether it was TF2 or EXF2 that generated the interrupt, and that bit will have to be cleared in software.
The Timer 0 and Timer 1 flags, TFO and TF1, are set at S5P2 of the cycle in which the timers overflow. The values are then polled by the circuitry in the next cycle. However, the Timer 2 flag, TF2, is set at S2P2 and is polled in the same cycle in which the timer overflows.
Symbol Position ' Function
EA IE.7 Disables all interrupts. If EA = 0,j no interrupt is acknowledged. If EA = 1, each interrupt source is individually enabled or disabled by setting or clearing its enable bit.
” IE.6 Reserved.
ET2 IE.5 Timer 2 interrupt enable bit.
ES IE.4 Serial Port interrupt enable bit.
ET1 IE.3 Timer 1 interrupt enable bit.
EX1 IE.2 External interrupt 1 enable bit.
ETO IE.1 Timer 0 interrupt enable bit.
EXO IE.0 External interrupt 0 enable bit.
User software should never write 1 s to unimplemented bits, because they may be used in future AT89 products.
IE0
Figure 6. Interrupt Sources
INTO
INT1
TF1
Tl Rl
TF2 EXF2
TFO
Microchip
28C64A
64K (8K x 8) CMOS EEPROM
FEATURES
¢ Fast Read Access Time”150 ns
¢ CMOS Technology for Low Power Dissipation
- 30 m A Active
¢ 100 uA Standby
¢ Fast Byte Write Time”200 us or 1 ms
¢ Data Retention >200 years
¢ High Endurance - Minimum 100,000 Erase/Write Cycles
¢ Automatic Write Operation
¢ Internal Control Timer
- Auto-Clear Before Write Operation
- On-Chip Address and Data Latches
¢ Data Polling
¢ Ready/Busy
¢ Chip Clear Operation
¢ Enhanced Data Protection
- Vcc Detector
- Pulse Filter
- Write Inhibit
¢ Electronic Signature for Device Identification
¢ 5-Volt-Only Operation
¢ Organized 8Kx8 JEDEC Standard Pinout
- 28-pin Dual-ln-Line Package
- 32-pin PLCC Package
- 28-pin Thin Small Outline Package (TSOP) 8x20mm
- 28-pin Very Small Outline Package (VSOP) 8x13.4mm
¢ Available for Extended Temperature Ranges:
- Commercial: 0*C to +70'C
DESCRIPTION
The Microchip Technology Inc. 28C64A is a CMOS 64K non¬volatile electrically Erasable PROM. The 28C64A is accessed like a static RAM for the read or write cycles without the need of external components. During a "byte write", the address and data are latched internally, freeing the micropro¬cessor address and data bus for other operations. Following the initiation of write cycle, the device will go to a busy state and automatically clear and write the latched data using an internal control timer. To determine when the write cycle is complete, the user has a choice of monitoring the Ready/ Busy output or using Data polling. The Ready/Busy pin is an open drain output, which allows easy configuration in wired-or systems. Alternatively, Data polling allows the user to read the location last written to when the write operation is com¬plete. CMOS design and processing enables this part to be used in systems where reduced power consumption and reli-ability are required. A complete family of packages is offered to provide the utmost flexibility in applications
PACKAGE TYPE
J Vcc i WE
IS Z
A1
DIP/ SOIC
PLCC
29j Ad 28 t A9 2j AH 261 NC 2sl OE 2li AtO 2VCE »j''W
i'lio*
]OE j AI0 !CE ; 1/07 ! 1/06 1/05 1/04 1/03
RDY/BSY C A12C A7 [ A6C A5C A4 L
A3 r
A2C AIL" AO L
i/oo r
i/oi C
i/os r
VssC
NC WE
Vcc
TSOP
RDY/BSY 8
A12 9
A7 10
A6 11
A5 12
A4 13
A3 14
NC WE
VSOP
A6 A5
Vss-Vcc-
Dala Protection Circuitry
Chip Enable/ Output Enable Control Logic
Data Poll
Auto Erase/Write Timing
¢ Pin 1 indicator on PLCC on lop of package
28 AH.
27 CE
26 10/
25 m
24 1 05
23 1:04
22 1/03
21 vss
20 1 02
19 1,01
18 1.00
1 7 AO
16 Al
15 «2
21 A10
¢' 20 CE
19 I/O 7
18 1/06
i 17 1/05
; 16 1/04
15 1/03
14 V=s
i 13 1/02
p n 12 I/O!
n 11 I/OO
10 AO
'. 9 A1
' 8 A
Program Voltage Generalion
Inpul/Output Bulfers
Y Galing
I6K 6.1 Ceil Matrix
1.0 ELECTRICAL CHARACTERISTICS
1.1 MAXIMUM RATINGS*
Vcc and input voltages w.r.t. Vss -0.6V to + 6.25V
Voltage on OE w.r.t. Vss -0.6V to+13.5V
Voltage on A9 w.r.t. Vss -0.6V to +13.5V
Output Voltage w.r.t. Vss -0.6V to VCC+0.6V
Storage temperature -65'C to +125"C
Ambient temp, with power applied -50"C to +95G
'Notice: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rat¬ing only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating con¬ditions for extended periods may affect device reliability.
TABLE 1-1: PIN FUNCTION TABLE
Name Function
AO - A12 Address Inputs
CE Chip Enable
OE Output Enable
WE Write Enable
I/O0 - I/07 Data Inputs/Outputs
RDY/Busy Ready/Busy
Vcc +5V Power Supply
VSS Ground
NC No Connect: No Internal Connection
NU Not Used: No External Connection is Allowed
TABLE 1-2: READ/WRITE OPERATION DC CHARACTERISTIC
DS11109G-page 2
© 1994 Microchip Technology Inc.
Address
CE
OE
Data
WE
FIGURE 1-1: READ WAVEFORMS
Notes: (1) tOFF is specified for OE or CE, whichever occurs first
(2) OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE
(3) This parameter is sampled and is not 100% tested
TABLE 1-4:
BYTE WRITE AC CHARACTERISTICS
AC Testing Waveform: Output Load: Input Rise/Fall Times: Ambient Temperature:
VlH = 2.4V; VlL = 0.45V; VOH = 2.0V; Vol = 0.8V 1 TTL Load + 100 pF 20 ns
Commercial ©: Tamb = 0'C to +70C Industrial (I): Tamb = -40°C to +85'C
Parameter Symbol Min Max Units Remarks
Address Set-Up Time tAS 10 ” ns
Address Hold Time tAH 50 ” ns
Data Set-Up Time tDS 50 ” ns
Data Hold Time tDH 10 ” ns
Write Pulse Width tWPL 100 ” ns Note 1
Write Pulse High Time ¦ fWPH 50 ” ns
OE Hold Time tOEH 10 ” ¢ ns
OE Set-Up Time tOES 10 ” ns
Data Valid Time tDV ” ¦ 1000 ns Note 2
Time to Device Busy tDB 2 50 ns
Write Cycle Time (28C64A) twc ” 1 ms 0.5 ms typical
Write Cycle Time (28C64AF) twc ” 200 us 100 |iS typical
Note 1: A write cycle can be initiated be CE or WE going low, whichever occurs last. The data is latched on the pos¬itive edge WE, whichever occurs first.
Note 2: Data must be valid within 1000ns max. after a write cycle is initiated and must be stable at least until Dh after the positive edge of WE or CE, whichever occurs first.
FIGURE 1-2: PROGRAMMING WAVEFORMS
Address
CE, WE
Data In
OE
Rdy/Busy
VlH VlL VlH VlL VlH VlL
VlH . VlL ¢
VOH -
Vol
X
1-tAS-f
tOES
-»-tDV¬
tAH ¦
tWPL
tDS ¦
twc¬
t DH
V
tOEH
¦ tDB -
Busy
Ready
DS11109G-page 4
© 1994 Microchip Technology Inc
F=/\IRGHIL-D
Discrete POWER & Signal Technologies
SEMICONDUCTOR rw
1N4001 -1N4007
Features
¢ Low forward voltage drop.
¢ High surge current capability.
-H
I (i iniii <2r4
l))iiiensi«m> m indk-Miiiini
!-* 1 tl .\W |JHM
(t.ii)7 i:".') (inxti i;mi
II.II.U ill N(>)
1.0 Ampere General Purpose Rectifiers Absolute Maximum Ratings* ta=25*c unless otherwise noted
Symbol Parameter Value Units
lo Average Rectified Current
.375 " lead length @ TA = 75UC 1.0 A
if(surge) Peak Forward Surge Current
8.3 ms single half-sine-wave
Superimposed on rated load (JEDEC method) 30 A
Pd Total Device Dissipation
Derate above 25°C 2.5 20 W
mW7' C
Rhja Thermal Resistance, Junction to Ambient 50 C/W
Tslg Storage Temperature Range -55 to +175 °C
Tj Operating Junction Temperature -55 to +150
T. = 25°C unless otherwise noled
These ratings are limiting values above which the serviceability of any semiconductor device may be impaired
Electrical Characteristics
Parameter Device Units
¦ 4001 4002- 4003 4004 4005 4006 4007
Peak Repetitive Reverse Voltage 50 100 200 400 600 800 1000 V
Maximum RMS Voltage 35 70 140 280 420 560 700 V
DC Reverse Voltage (Rated Vr) 50 100 200 400 600 800 1000 V
Maximum Reverse Current
@ rated Vr Ta = 25°C . TA=100°C 5.0 500 uA
LlA
Maximum Forward Voltage @ 1.0 A 1.1 V
Maximum Full Load Reverse Current, Full Cycle . Ta' = 75°C 30 uA
Typical Junction Capacitance VR = 4.0 V, f = 1.0 MHz 15 pF
<E1998 Fairchild Semiconductor Corporation
Typical Characteristics
General Purpose Rectifiers
(continued)
L730
POSITIVE VOLTAGE REGULATORS
* OUTPUT CURRENT UP TO 1.5 A
. OUTPUT VOLTAGES OF 5; 5.2: 6; 8; 8.5; 9;
12; 15; 18; 24V . THERMAL OVERLOAD PROTECTION . SHORT CIRCUIT PROTECTION
* OUTPUT TRANSITION SOA PROTECTION
DESCRIPTION
The L7800 series of three-terminal positive regulators is,available in TO-220 ISOWATT220 TO-3 and D^PAK packages and several fixed output voltages, making It useful in a wide range of applications These regulators cart provide iocai on-card regulation, eliminating the distribution problems associated with single point regulation. Each type employs internal current limiting, thermal shut-down and safe area protection, making it essentia!!1/ indestructible. If adequate heat sinking is provided, they can deliver over 1A output current. Although designed primarily as fixed voltage regulators, these devices can be used with external components to obtain adjustable voltages and currents.
f-- '¦ i A, ;s
BLOCK DIAGRAM
INPUT
5CR<X£-ELFWEfcT
OUTHtJt
STARTING CIRCUIT
OJR« GENFT 1EMT

HFFEB&ICE
30A
PROTECTION
PROJECTION
i]
*- 03
1/25
L7S00
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value
V, DC Input Voltage (for V0 = 5 to 18V) (forVo = 20,24V) 40
lo Output Current ¦: :v-'v iir:
Plot Power Dissipation
ini^r;;/iHv i'n
Top Operating Junction Temperature Range (for L7800)
{for L7S00C;
Ts!a Storage Temperature Range
Ur.it
THERMALDATA
Symbol Parameter D PAK rO-220 ji$OWA"f722C; TO-'3 | ¢,;¢¢¢!
Rthj-case Thermal Resistance Junction-case Max ' ¦-' t
3 ! 3 r 4
Rthj-amb Thermal Resistance Junction-ambient Max 62.5 j ":r: j '".V
CONNECTION DIAGRAM AND ORDERING NUMBERS (top view)
1
i "
3

/n”cri
j^r. ouipj;
Z73
{Ci
TO-220 & ISOWATT220
D' PAK
Type TO-220 D'PAK (') iSOVVATT220 TO-3
1.7605
L7805C L7805CV L7805CD2T L7805CP L7805C I
L7852C ¦ L7852CV L7852CD2T L7852CP L7852C"i
L7806 L780GT
L7806C L7806CV L7806CD2T L780SCP I.7306C!
L.7808 L 7808 V
L7808C L7608CV L7808CD2T L7608CP L.7808CV
L7885C I.7885CV L7885CD2T L7885CP L7885C:
L7809C L7809CV L7809CD2T L7809CP L7809CT
L7812 L"'f(-2T
. L7812C L7812CV L7812CD2T L7812CP L7812CT
L.7815 L78151
L7815C L7S15CV L7815CD2T L.7815CP L7S15G:
L7818 L7S13i
L7818C L7813CV L7818CD2T L781SCP I.7818CT
L7820 1.78201
L7820C L7820CV L7820CD2T L7820CP L7820C1
1.7824 L7324T
L7824C L7824CV L7824CD2T L7824CP L7324CT
O AVAILABLE IN TAPE AND RESL WITH "-TR" SUFFIX
2/2£