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VLSI Realization Process
Intel Processor Sizes
Full Custom Design
ASIC Design
FPGA Architecture - Layout
Island FPGAs
Array of functional units
Horizontal and vertical routing channels connecting the functional units
Versatile switch boxes
Example: Xilinx, Altera
Row-based FPGAs
Like standard cell design
Rows of logic blocks
Routing channels (fixed width) between rows of logic
Example: Actel FPGAs
VHDL
VHDL:
WELL SUITED FOR PLD,CPLD,FPGA AND ASIC ALSO.
CAPACITY 500 TO 1LK GATES
BRINGS LARGER CIRCUIT DESIGN TO MARKET RAPIDLY
COMPONENT REUSABILITY
STANDARD LANGUAGE (IEEE)
VHDL AN INTRODUCTION
VHDL is a product of VHSIC program of US Department of Defense(DoD).
VHDL--Very High Speed Integrated Circuit Hardware Description Language
VHDL is an industry standard for the description, Modeling and Synthesis of digital circuits and systems.
VHDL
To model the digital system at any level of abstraction from architecture to gate level.
Sequential language + Concurrent L+ net-list L + Timing specification + Waveform generation => VHDL
It contains elements that can be used to describe the behavior, structure of the digital system with the provision for specifying its timing explicitly.
VHDL AN INTRODUCTION
Why Use VHDL (Advantages)
Power and Flexibility
Device independent design
Portability
ASIC Migration
Quick time to market and low cost
Why Use VHDL (Advantages)
Power and Flexibility *Powerful language *Multiple level of design description for controlling design *Creation of reusable components *One language for design & simulation
Device independent design *No need to consider any device while designing

* allows multiple style of design description
Portability * Since VHDL is std one,design can be taken from one simulator/ synthesizer/ platform to another
ASIC Migration
Quick time to market and low cost *VHDL-PLD’s pair facilitates a speedy design process * Powerful vehicle to bring the product to market in record time
Disadvantages
Less control of defining gate level implementation.
The implementation created by synthesis tool is inefficient.
The quality of synthesis varies from tool to tool.
VHDL for Design Synthesis
Define the design requirements
Describe the design in VHDL(formulate and code the design)
Simulate the source code.
VHDL for Design Synthesis
Synthesis
Is a process of translation & optimization
Process by which netlist or equations are created from design descriptions.
It is technology specific.
It translates the behavioural descriptions to a register transfer level descriptions (RTL).
Design process Comparison
Design process Comparison
VERILOG ALSO
SIMPLER THAN VHDL
BUT VHDL IS THE BEST CHOICE FOR COMBINED PURPOSE OF DOCUMENTATION, SYNTHESIS, SIMULATION.
History
A team IBM Texas Instruments Intermetrics were first awarded the contract by DoD to develop a version of language in 1983.
Vesion VHDL 7.2 released in 1985
IEEE std gat in 1987 as IEEE Std 1076-1987
It was also recognized as ANSI Std.
Upgraded and again got IEEE Std 1076-1993
History
DoD also standardized the Value logic as Nine value logic from 46, 7, 4 values were used by different companies.
Capabilities
VHDL can be used as an exchange medium between Chip vendors , CAD and CAE tool users.
Any model can be designed hierarchically.
It supports Top-down , Bottom-up and mixed design
Models written VHDL can be verified using VHDL Simulator.
Capabilities
It supports both synchronous and asynchronous timing models
Various digital modeling techniques such as: FSM, Algorithmic descriptions, and all boolean equations can be modeled.
It is publicly available, human readable, machine readable and it is not proprietary
Capabilities
No limitation in size of the design
It is an IEEE and ANSI Standard
Modeling is much easier.(Reusability feature)
Physical parameters can be described very naturally. Ex. Deleays, timings etc.


VHDL * Unlike C,FORTRAN,PASCAL etc..Where algorithm-Sequence of data manipulation * VHDL is different, where it is used for mimicking the behavior of some physical system such as digital circuits. * It describes the system and then simulator executes the same

1. System Description
2.Events, Propagation Delay, Concurrency
3.Waveforms and Timings
4. Signal Values
5. Shared Signals
6. Discrete event Simulator model
Design(Conventional)


COMPLETE VHDL PROGRAM
Library clause
Use clause
Entity
Architecture
Features
Library
Statements
Sequential
Concurrent
Generic
Subprogram
Procedure
Function
Package
Configuration

Entity
ENTITY
Entity half_adder is port (a,b:in bit; sum,carry : out bit);
end half_adder;
ENTITY
Entity half_adder is port (a,b:in std_ulogic; sum,carry : out std_ulogic);
end half_adder;
ENTITY
Entity half_adder is port (a,b:in std_logic; sum,carry : out std_logic);
end half_adder;

4 to 1 mux
ENTITY
Entity mux4 is port (I0, I1,I2,I3:in std_logic_vector(7 downto 0); sel : in std_logic_vector(1 downto 0); z :out std_logic_vector(7 downto 0));
end mux4;

D flip flop
ENTITY
Entity d_ff is port (D,clk,R,S :in std_logic; Q,Qbar : out std_logic);
end d_ff;

ARCHITECTURE
Architecture arch_name of entity_name is -- place declaration here begin -- place description here end arch_name;
ARCHITECTURE
Architecture arch_half_adder of half_adder is -- place declaration here begin sum <=(a xor b) after 5ns; carry<= (a and b) after 5ns; end arch_half_adder;

COMPLETE VHDL PROGRAM
Library IEEE;
use IEEE.std_logic_1164.all
Entity half_adder is port (a,b:in std_logic; sum,carry : out std_logic);
end half_adder;

Architecture arch_half_adder of half_adder is -- place declaration here begin sum <=(a xor b) after 5ns; carry<= (a and b) after 5ns; end arch_half_adder;
back


Vhdl Part –2
Identifiers
Data Objects
Data types
Operators
Identifiers
It is a name of an object or is a reserved word.
Identifiers are made up of alphabets, numerals and / or under score characters.
Two types Basic and Extended


Extended Identifier
Sequence of characters written in between two back slashes
Any of allowable characters can be used including ., !, @, ‘, $, etc
case sensitive
no such rules like in basic type

Legal extended identifiers
\test\
\_-45\
\2input_o/p\
\process\ - distinct fro keyword process
\$.~*\ - any symbol can be used
\TEST\ - distinct from above \test\
VHDL syntax
not case sensitive.
semicolon for termination of a statement.
-- the start of a comment. It extends till the end of the line
strongly typed language.
Data objects
It may comes under one of the following classes:
Constant
Variable
Signal
File



Signals
Signals represent data values on physical data lines. Signals are wires and are used to inter connect components.
Ports are signals .
A signal can represent the state of memory elements.
Signals do not change instantaneously
Signal count : bit_vector(3 downto 0) ;
Initial values may be assigned to signals but are ignored for synthesis
Classification of data types
Scalar: Types whose values are single entities
composite : values are complex objects. Array and Record types.
Access: that provides access to other types thro pointers.
File: that provides access to files.
Data Types
Scalar types :
There are 4 categories of scalar types.
Enumeration type
Integer type
Floating point type
Physical type
Subtype
It is possible to derive another type called subtype from predefined or user defined types.
Subtype can be derived for any base type.
Ex.
Subtype MY_INTEGER is INTEGER range 2 to 20;
here base type is INTEGER and derived type is MY_INTEGER

Physical type
It contains value that represent measurements of some physical quantity like time, length, voltage or current
values are represented as integer multiples of base unit
type CURRENT is range 0 to 1E9 units nA; -- Base unit uA = 1000 nA; -- Derived units mA = 1000uA; Amp = 1000mA; end units;
COMMON DATA TYPES
Bit : A 1 bit value represents a wire.
Bit_Vector : An array of bits.
Std_ulogic bit with 9 value logic
Std_ulogic_vector array of such bits
Std_logic bit with 9 value logic which are resolved type
Std_logic_vector array of such bits
Boolean : A true or false value.
Std_ulogic
The type std_ulogic defines a 9 value logic system.
Type std_ulogic is (‘U’, ‘X’, ‘0’, ‘1’, ‘Z’,’W’, ‘L’, ‘H’, ‘-’) ;
U - un initialized
X - forcing unknown
0 - forcing 0
1 - forcing 1
Z - High impedance

W - Weak unknown
L - Weak 0
H - Weak 1
‘-’ - don’t care
The values 0, 1 , L, H, Z & don’t care are supported by synthesis.
The IEEE 1164 standard defines arrays of std_logic as std_logic_vector.

BACK
Assignment Statements
Variable assignment
Replaces the current value of the variable by a new value determined by an expression.
Variable assignment is instantaneous.
:= delimiter is used to define variable assignment.
Current_state := s4;
Signal Assignment
Schedules a new value for a signal to occur at some future time.
The current value of a signal is never changed.
X1 <= ‘1’ after 5 ns;
d2 <= ‘1’; _ _ Delta delay.
<= indicates signal assignment.
Signal vs Variable
Variables are declared within process,subprograms.
Signals are declared within architecture bodies. They are used as ports
for VHDL entities.
Signal assignment <=
Variable assignment :=

Variable assignment is immediate;
Signal assignments are delayed.
Signal requires more overhead in terms of storage and simulation time than Variables.
OPERATORS
Types:
1. Logical Operators
2. Relational
3. Shift
4. Adding
5. Multiplying
6. Miscellaneous back


Sequential statements



Proc1: Process (a,b,c)
Begin
X <= a and b and c;
End process;


Proc 2: Process
Begin
X <= a and b and c;
Wait on a,b,c;
End process;
A wait statement can also be used to suspend a process.Synthesis software supports ‘wait ‘ statements only at the beginning or at the end of the process.

Proc 3: Process (a,b,c)
Begin
X <= a and b and c after 5 ns. ;
End process;

After clauses are usually ignored by synthesis software.
IF - THEN - ELSE
It is used to select a statement to execute based on a Boolean evaluation (true or false) of a condition or a set of conditions.
If ( condition) then set of statements; else if (condition ) then set of statements;
else
set of statements;
end if;

Multiplexer using if-then-else
Library IEEE;
Use IEEE.std_ logic_1164.all;
Entity mux is
Port (a,b,c,d: in std_logic;
s : in std_logic_vector(1 downto 0);
y :out std_logic);
end mux;

Architecture mux_a of mux is
Begin
process(a,b,c,d,s)
begin if (s = “ 00”) then y <= a; elsif (s = “ 01”) then y <= b; elsif (s = “ 10”) then y <= c; else y <= d; end if;
end process;
end mux_a;

Case - when
Case statements are used to specify a set of statements to execute based on the value of a given selection signal.
Case selection_signal is
when value1 of selection_signal =>
set of statements1 ; ...
when value n of selection_signal =>
set of statements x ;
When others => set of statements;
end case;


Loop statements
To iterate thro a set of Sequential statements.
Syntax
[loop_label :] iteration_schemes loop
Seq. st
end loop [loop_label];
3 types of iteration_schemes :
for loop
While loop
simple loop
For loop
For identifier in range
loop
seq. st.
end loop;
Ex:
variable fact :integer :=1;
variable n:integer:=10;
for num in 2 to n loop
fact:= fact*num;
End loop;


Assert statement
Has three optional field
The condition must evaluate to a Boolean Value( TRUE or FALSE).
If it is false an assertion violation has occurred.
The expression specified in the report clause must be of predefined type STRING and is the message to be reported when assertion violation occurred.
Useful in modeling constraints of an entity
A condition can be checked and report if it fails
Syntax
[Assert_label:] assert condition
[report message string]
[severity severity_level];
Assert statement
The Severity_level type is specified in the STANDARD package .It contains four values:
NOTE
WARNING
ERROR
FAILURE
WAIT STATEMENT
It stops simulation temporarily till condition is true
Syntax
wait on sensitivity_list;
wait until condition;
wait for time_expn;
wait on sensitivity_list until condition
for time_expn;


Examples:
wait on d, clk;
wait until sel=“0011’’;
wait for 20 ns;
wait on d for 20 ns;
wait on clk until count<100
for 100 ns;
The wait for construct is not ynthesizable.
wait until clk = ‘0’ and clk’event;
This is used to synthesize registers (negative edge trigged flip-flops).





Null statement
Null;
it does not cause any action to take place.
execution continues with next st.

back

Concurrent statements
Concurrent statements lie between the ‘begin ‘ and ‘end’ portion of an architecture.
They are executed in parallel.
Concurrent signal assignment statements
Selective signal assignment
Conditional signal assignment
Process statement
Component Instantiation
Generate statement
Concurrent statements
The block and process are concurrent statements.

Signal assignments & procedure calls are concurrent provided they do not reside in a process statement.

The order of the concurrent statements does not have an effect on the logic that is described.
Concurrent signal assignment
Architecture concurrent of half_adder is
begin
sum <= a xor b;
carry <= a and b;
end concurrent;
With_ select_when
Provides selective signal assignment
A signal is assigned a value base on the value of a selection signal
with selection_signal select
signal_name <=
value_a when value_1 of selection signal, value_b when value_2 of selection signal,
value_c when value_3 of selection signal, value_d when last value of selection signal;
-
Mux (with_ select_when)
Library ieee;
use ieee.std_logic_1164.all;
entity mux421 is
port( a,b,c,d : in std_logic;
s : in std_logic_vector(1 downto 0);
o : out std_logic);
end mux421;


Architecture mux_a of mux421 is
begin
with s select
x <= a when”00”,
b when”01”,
c when”10”,
d when others;
end mux_a;
When_else
Conditional signal assignment
A signal is assigned a value based on a condition
signal_name <=
value_ a when condition1 else
value_b when condition2 else
value_X;
Conditional signal assignment
Architecture mux421_a of mux421 is
begin
o <= a when(s = “00”) else
b when(s = “01”) else
c when(s = “10”) else
d;
end mux421_a;

GENERATE statements
A mechanism for iterative or conditional elaboration of a design.

It is used to specify a group of identical components.
Assertion Statement
A statement that checks that a specified condition is TRUE and reports an error if it is not.
Syntax
assert condition
report string
severity severity_level
Modeling
1. Data Flow – set of concurrent St.
2. Behavioral- Process & Seq . st.
3. Structural-set of components
4. Combination of above
Half adder
Data flow
Architecture arch_half_adder of half_adder is -- place declaration here begin sum <=(a xor b) after 5ns; carry<= (a and b) after 5ns; end arch_half_adder;

Behavioral
Architecture barch_half_adder of half_adder is begin
Process(a,b)
begin if a=b then sum <=‘0’;
else sum <= ‘1’;
end if;
If a=‘1’ and b=‘1’ then carry<=‘1’;
else carry<= ‘0’;
end if;


end process; end barch_half_adder;

Signals can’t be declared within the process
structural
Architecture sarch_half_adder of half_adder is
component xor2 port (x,y:in std_logic; z:out std_logic); end component;
component and2 port (a,b:in std_logic;
c:out std_logic); end component;
begin
x1: xor2 port map (a,b,sum);
a1: and2 port map (a,b,carry);
End sarch _half_adder ;


Mixed modeling
Entity fa is
port(a,b,cin :in std_logic;
sum,cout :out std_logic);
End fa;
Architecture fa1 of fa is
component xor2 port (x,y:in std_logic; z:out std_logic); end component;
Signal s1: std_logic;
Begin
x1: xor2 port map (x =>a,y =>b,z => s1);

Process(a,b,cin)
variable t1,t2,t3 : std_logic;
begin
t1:=a and b;
t2:=b and cin;
t3:=cin and a;
cout<=t1 or t2 or t3;
end process;
sum<= s1 xor cin;
End fa1;

Test bench
library ieee;
use ieee.std_logic_1164.all;
entity fa_tst is
end fa_tst;
architecture arcfatst of fa_tst is
component fulladder
port(a,b,cin:in std_logic;
sum,cout:out std_logic);


end component;
signal p,q,r,s,t td_logic;
begin
f1:fulladder port map(a=>p,b=>q,cin=>r,sum=>s,cout=>t);
process
Begin
p<='1';q<='1';r<='1'; wait for 50 us;
p<='0';q<='0';r<='0'; wait for 50 us;
end process;
end arcfatst; back

Aoi logic

library ieee;
use ieee.std_logic_1164.all;

entity test1 is
port (a,b,c,d:in std_logic;
z:out std_logic);
end test1;

architecture a1_test1 of test1 is
signal s1,s2,s3td_logic;
begin
process(a,b)
begin
s1 <= a and b;
s2<=c and d;
s3<=s1 or s2;
z<=not s3;
end process;
end a1_test1;
-- *******TEST BENCH ***********
library ieee;
use ieee.std_logic_1164.all;
entity test1_tst is
end test1_tst;
architecture a1_test1_tst of test1_tst is
component test1 port(a,b,c,d:in std_logic;
z:out std_logic);
end component;
signal a1,b1,c1,d1,z1td_logic;
begin
test10: test1 port map(a=>a1,b=>b1,c=>c1,d=>d1,z=>z1);
process
begin a1<='0';b1<='0';c1<='0';d1<='1'; wait for 5 ns;
a1<='0';b1<='1';c1<='1';d1<='1'; wait for 5 ns;
end process;
end a1_test1_tst
Synthesised-RTL schematic of FPGA –Xilinx_3000 device
Critical path
CONFIGURATION
Many approaches are there to model the operation of a digital circuits such as behavioral and structural.
In these approaches(descriptions) , at a particular instant only one model is utilized by the main model (component).
CONFIGURATION specifies which model is associated with the main model.
The process describing the association in the configuration is called BINDING
In the absence of configuration default binding rules apply.
Two forms:
1. Configuration specification
2. Configuration decleration
default Binding Rules:
When there is no configuration information: If the entity name is same as the component name, then this entity is bound to the component. No need to go for configuration in the case of same name.
Configuration
A configuration declaration is a primary design unit used to bind entity statements to particular architecture bodies to form components of a design.
Configuration
Selects architecture
Binds components
Resides in a design library
Configuration specification:
Part of the architecture
Can be given within the architecture
Configuration Declaration
Separate design unit
A configuration is a construct that defines how component instances are bound to design entities in order to describe how design entities are put together to form a complete design.