06-06-2012, 11:50 AM
Closed loop timing
Closed loop timing.ppt (Size: 624.5 KB / Downloads: 1)
Bundled closed loop timing
Signal AD and ref signal Aclk transition tncq after each transition on Tclk
Vector BD and reference Bclk transition tnAB later.
Timing loop locks the quadrature clock Qclk to Bclk with offset lag equal to aperture offset ta0 of phase detector of flip-flop
This places the receive clock, Rclk which is offset from Qclk by П/2
Aperture is exactly centred on the eye of data vector BD.
Which of these elements of timing uncertainty are cancelled?
All repeatable portions of skew are cancelled: tx/rx clock, tx output delay, line delay, rx aperture offset.
Others are NOT cancelled (skew between individual flip-flops and their tx/rx clocks, for example)
Jitter is never canceled as it is not repeatable from cycle to cycle.
Now which of these elements of timing uncertainty are
cancelled?
All repeatable portions of skew are still cancelled: tx/rx clock, tx output delay, line delay, rx aperture offset. We also cancel the 90 degree offset
Others are NOT cancelled (skew between individual flip-flops and their tx/rx clocks, for example)
transmit clock jitter is almost completely eliminated as we use the same edges for clocking out of the tx and into the rx. Jitter between individual flip-flops is still there, however.
Reducing jitter with a PLL
PLL based on stable VCO acts as LPF for phase.
Attenuates high frequency components of jitter, thise above the cutoff of loop filter
By setting cut off of the loop properly, a PLL can be used to clean up a noisy clock signal which significantly reduces the jitter
Oversampling clock recovery
Instead of tracking clock signal which involve DLL or PLL a free running local clock can be used to recover the clock
Example 3X oversampling
Input can be recovered b selecting one of every 3 bits, does not matter which one.
If input sequence is 1011001
then oversampled 3x sequency.
