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1. INTRODUCTION
1.1. Evolution of computer aided designs:
VHDL is a hardware description language intended for documenting and modeling digital System ranging from a small chip to a large system. It can be used to model a digital system at any level of abstraction ranging from the architectural level down to the gate level.
The language was initially developed specially for department of defense VHSIC (very high speed integrated circuits) contractors. However, due to an overwhelming need in the industry For a standard hardware description language, the VHSIC hardware description language (VHDL) was selected and later approved to become an IEEE standard called the IEEE std 1076-1987. The language was updated again in 1993 to include a number of clarifications in addition to a number of new features like report statement and pulse rejection limit.
Digital circuit design has evolved rapidly over the last 25 years. The earliest digital circuits were designed with vacuum tubes and transistors. Integrated circuits were then invented where logic gates were placed on a single chip. The first integrated circuit (IC) chips were SSI (small scale integration) chips where the gate count was very small. As technologies became sophisticate, designers were able to lace circuits with hundreds of gates on a single chip.
The traditional design methods are convenient as long as the system is simple and gates involved in final implementation are limited for larger systems, inputs and outputs are more and obtaining the truth table or table can be difficult if not impossible and the processes started getting very complicated and designers felt the need to automate these processes. Computer aided design (cad) techniques began to evolve.
Chip designers began to use the circuit and logic simulation techniques to verify the functionality of building blocks of the order of about 100 transistors. The circuits were still tested on the board, and the layout was done on paper or by hand on graphic computer terminal.
With the advent of VLSI (very large scale integration) technology, designers could design single chips with more than 1, 00,000 transistors. Because of complexity of these circuits, it was not possible to verify these circuits on a breadboard. Computer aided techniques became critical for verification and design of VLSI digital circuits.
Computer programs to do automatic placement and routing for circuit layouts also became popular. The designers were now building gate level digital circuits manually on graphic terminals.
They would build small building blocks and then derive higher- level blocks from them. This process would continue until they had built the top-level block. Logic simulators came into existence to verify the functionality of these circuits before they were fabricated on chip.
As designs got larger and more complex, logic simulation assumed an important role in the design process. Designers could iron out functional bugs in the architecture using simulation, before chop was designed further.
1.2. Emergence of HDLs:-
For longtime, programming languages such as FORTRAN, PASCAL and C were being used to describe computer programming that was sequential in nature. Similar in the digital field, designers felt the need for a standard language to describe digital circuits. Thus, hardware description languages (HDLs) came into the existence.
HDL allowed the designers to model concurrency of processes found in hardware elements. Hardware description languages such as verilog HDL and VHDL became popular. Verilog HDL originating in 1983 at gateway design automation. Later, VHDL was developed under contract from DARPA. Both verilog and VHDL Simulators to simulate large digital circuits quickly gained acceptance from designers.
Even though DHLS were popular for large verification, designers had to manually translate the HDL based design into a schematic circuit with interconnections between gates. The advent of logic synthesis in the late 1980s changed the design methodology radically. Digital circuits could be described at a register transfer level (RTL) by use of a HDL. Thus, the designers had to specify how the data flows between registers and how the design processed the data.
Logic synthesis tools from the RTL description automatically extracted the details of gates and their interconnections to implement the circuit. Thus, logic synthesis pushed the HDLs into forefront of digital design. Designers no longer had to manually place gates to build logic circuits. They could describe complex circuits at an abstract level in terms of functionality and data flow by designing those circuits in HDLs. Logic synthesis tools would implement the specified functionality in terms of gate interconnections.
HDLs also began to be used for system-level design. HDLs were used for simulation of system boards, inter connect buses, FPGAs (Field Programmable Gate Arrays) and PALs (Programmable Array Logic). A common approach is to design each IC chip using an HDL, and then verify system functionality via simulation.
1.3. TYPICAL DESIGN FLOW:
Typical design flow for designing VLSI IC circuits is shown in figure
1.4. IMPROTANCE OF HDLs:
HDLs have many advantages compared to traditional schematic-based design:
Design can be described at a very abstract level be use of HDLs. Designers can write their RTL description without choosing a specific fabrication technology. Logic synthesis tools can automatically convert the design to any fabrication technology. If a new technology emerges Designers don’t need to redesign their circuit. They simply input the RTL description to the logic synthesis tools and crate a new gate-level net list. Using the new fabrication technology.
The logic synthesis tools will optimize the circuit in area and timing for the new technology. By describing designs in HDLs, functional verification of the design can be done early in the design cycle. Since designers work at the RTL level, they can optimize and modify the RTL description until it meets the desired functionality.
Most design bugs are eliminated at this point. This cuts down design cycle time significantly because the probability of hitting a functional bug a later time in the gate-level net list of physical layout is minimized.
Designing with HDLs is analogous to computer programming. A textual description with comments is an easier way to develop a circuit.
This also provides a concise representation of the design, compared to gate-level schematics. Gate-level schematics are almost in comprehensible for very complex design.
HDLs are almost certainly a trend of the future. With rapidly increasing complexities of digital circuits and increasingly sophisticated CAD tools, HDLs will probably be the only method for large digital designs. No digital circuit designer can afford to ignore HDL-based design.
