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Contents
Introduction
Delay Locked Loop
Proposed Reversible SAR
RSAR Lock-in Strategy
Architecture of RSAR DLL
1. 11-Bit RSAR controller
2. Control-Bit Selection Circuit
3. DCDL
4. Timing Controller
Implementation & Testing
Conclusion
References

Introduction
This brief proposes a novel circuit architecture
of an 11-bit RSAR-controlled All Digital DLL.

It could achieve adaptive bandwidth in a wide
operation range by utilizing the modified binary
search algorithm of the RSAR scheme.

It is fast locking because it finds the suitable
delay range first and the successive
approximation register process next.

Delay Locked Loop (DLL)
Nowadays many high speed systems adopt DLL and PLL to solve clock-skew problem.

DLL has better jitter performance than PLL , since phase error is not accumulated in the noisy environment.

VCO in PLL is replaced by a Delay Line in DLL, which makes it more stable.

Digital Controlled Delay Line (DCDL) is more suitable in system-on-a-chip design.



Digital DLL is developed from analog DLL by
substituting Voltage Controlled Delay Line with
Digital-Controlled Delay Line.

Charge pump and low filter in analog DLL is
replaced by certain digital control circuits.

Different controlling schemes of digital DLL
are Counter-Controlled Scheme, Time-to-Digital
Scheme and SAR-Controlled Scheme.

SAR DLL scheme has a short lock-in time due
to the adoption of binary search algorithm.

The draw backs of conventional SAR DLL are
its narrow frequency range and harmonic lock.
The maximal time period of input clock signal
is given by
To avoid harmonic locking, the time period of
input clock should be

Combining both, the frequency limitation of
the input clock could be expressed as
The highest frequency of the input clock is
smaller than 3 times of the lowest one.


Proposed Reversible SAR (RSAR)

This brief proposes a Reversible SAR scheme
to keep the fast-locking characteristic of SAR
DLL, widen the frequency range etc.

Unable-to-lock and harmonic-lock problems
are eliminated by doubling the delay line every
step to find the operating frequency range.

RSAR scheme takes only 21 steps to lock in.


Rather than starting from the middle of the
delay line, this scheme starts from the lowest
bit to search the suitable delay line.

If Tint is larger than TCLK, then harmonic lock is
bound to happen. Thus its relation is given by

RSAR Lock-in Strategy
Initially all N-bits are low, K=0.

Set last k-bit high and check whether the
delay range is suitable or not.

If not, K will be incremented and repeat the
second step.

After reaching the suitable range, K-bit SAR
process starts and lock is attained.

Architecture of RSAR DLL
The architecture of the whole proposed RSAR
DLL is shown in the fig.

The division ratio of 2 is chosen for the divider
to minimize the lock-in time and to make sure
that the control word is ready before the next
rising edge of CLKin because of latency of the
DLL.

The 11-bit SAR Controller could perform the
SAR process from any bit.


The control word does not directly come from
the RSAR controller but from the control-bit
selecting circuit that could find the suitable
delay range in the beginning and search the
highest wrong bit when the dead lock problem
happens.

At worst, it takes 11 steps to find the suitable
delay line and 11 steps to perform the SAR
process with one step overlap, so the total
lock-in steps are 21 and total cycles are 42
(Since there is a division ratio 2).

1. 11-Bit RSAR Controller
The conventional SAR could only perform the
SAR process from the highest control bit in a
top-down order.

To make it able to perform the SAR process
from any bit, the new RSAR Control Unit can
set by s[i] and reset by r[i].

Nres is down if delay range is no enough.


2. Control-Bit Selecting Circuit
When DLL begins to search for the highest
wrong bit, Nres is low, and the shift register
is activated.

Ncomp tells c whether the delay is enough
or not.

After the SAR start bit is found, Nres is high
and b[i] becomes a[i].

3. DCDL
DCDL is Digital Controlled Delay Line.

Its constructed by the lattice delay line and
have a small intrinsic delay Tint.

4. Timing Controller
The signal Start is high to set a, b and c and
reset d so ctrl and Nres are both 0.

When Start falls down, the 11-bit RSAR
controller and control-bit selector are enabled.

Ncomp is high to increase the delay range to
search the suitable delay line in the beginning,
and it is comp in other cases.

Implementation & Testing
Its implemented in SMIC 0.13µm CMOS
technology
Locked state at 30 MHz has
mean peak-to-peak jitter of
about 60ps.
Locked state at 1 GHz has
mean peak-to-peak jitter of
about 30ps.

Conclusion
A 30MHz-1 GHz all-digital 11-bit RSAR DLL
has been proposed.
With the improved RSAR scheme, the frequency
range is greatly expanded.
This is applicable for high speed memories, such
as QDR II Memory and Dual Data Rate memory,
which sometimes has a clock-skew problem at
high frequencies.
The proposed RSAR DLL can be used in
ultra-wide band systems.

References
“Jitter Transfer Characteristics of Delay-Locked Loops
—Theories and Design Techniques”
M.-J. Edward Lee, William J. Dally, Trey Greer, Hiok-Tiaq Ng,
Ramin Farjad-Rad, John Poulton and Ramesh Senthinathan

“A Wide-Range and Fast-Locking All-Digital Cycle-Controlled
Delay-Locked Loop”
Hsiang-Hui Chang and Shen-Iuan Liu

“A 40–550 MHz Harmonic-Free All-Digital Delay-Locked Loop
Using a Variable SAR Algorithm”
Rong-Jyi Yang and Shen-Iuan Liu