PRESENTED BY
S.ELANGO
P.C. KISHORE KUMAR

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A 130nm CMOS to Minimize area and quantization noise in frequency synthesizer using offset PLL
ABSTRACT
 It achieves low-noise .
 OPLL highly suppresses the quantization noise from the delta-sigma modulator.
 It consumes low power by employing charge-recycling
technique in the sub-PLL.
 Synthesizer implemented in 0.13 ȗm
 CMOS process achieves 9 dB of noise reduction compared to a conventional PLL while consuming 3.2 mW of power.
INTRODUCTION
 Delta-sigma modulators (DSM) -used in modern communication systems due to their fine frequency resolution.
 Fractional-N frequency synthesizer using offset-PLL (OPLL) - quantization noise suppression .
 Power consumption is greatly reduced by using charge-recycling
Technique.
CHARACTERISTIC APPLICATION
 It widely used in in radio
telecommunications
computer and other electronic applications.
 They may generate stable frequencies, recover a signal from a noisy communication channel.
 Distribute clock timing pulses in digital logic designs such as microprocessors Since a single integrated circuits can provide a complete phase-locked-loop building block.
EXISTING WORK
• It uses single PLL,
• It is implemented in 180nm technology.
• Power consumption is 26.8mW
• Supply Voltage is 2v
• Chip area is 0.85mm2 .
DESCRIPTION
 Consists of a main and a sub-PLL
 Main PLL contains a mixer instead of a divider-- which receives
its input from the fractional-N sub-PLL.
 The output of the mixer is fed to a low-pass filter where only the difference of
the two mixer input frequencies passes through , then fout
Where
N-fractional division ratio of the sub-PLL
M-integer division ratio of the main-PLL
Fref1 & fref2 -- reference frequency of the main and the sub-PLL
To lock initial frequency of the VCO1 must be larger than fvco/2- fref
for the OPLL