ABSTRACT
As power consumption of the clock tree in modern VLSI designs
tends to dominate, measures must be taken to keep it
under control. This paper introduces an approach for reducing
clock power based on clock gating. We present a methodology
that, starting from an RTL description, automatically
generates a set of constraints for driving the construction of
the clock tree by the clock synthesis tool. The methodology
has been fully integrated into an industry-strength design
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