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Title: Integrating Structural Design and Formal Methods in RealTime System Design Page Link: Integrating Structural Design and Formal Methods in RealTime System Design - Posted By: computer science crazy Created at: Thursday 03rd of September 2009 07:07:58 PM | |||
Formal methods have been advocated as one of those techniques that can produce highquality software and hardware systems that has been demonstrated to come in ontime, within budget, and satisfy procurer requirements. They are, however, perceived to be difficult to use and unsuitable for presentation to nonspecialists. In addition, they have been criticized for paying too little attention to the system development process. | |||
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Title: Formal Modelling of Multi-Agent Systems Page Link: Formal Modelling of Multi-Agent Systems - Posted By: computer science crazy Created at: Tuesday 24th of February 2009 04:26:28 AM | |||
Multi-agent systems exhibit highly dynamic behaviour within dynamic environments. Modelling of individual agents within such systems demands considering both evolving data structures and the control over their internal changing states. In addition, modelling of the overall system implies modelling of the agents configuration, including their ability to exchange messages as well as the ability to re-structure their formation over time. This is particularly the case with biological multi-agent systems, such as colonies of ants or bees, flocks of ..............etc | |||
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Title: Integrating Structural Design and Formal Methods in RealTime System Design Page Link: Integrating Structural Design and Formal Methods in RealTime System Design - Posted By: Computer Science Clay Created at: Sunday 01st of March 2009 03:55:50 PM | |||
Integrating Structural Design and Formal Methods in RealTime System Design | |||
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Title: Formal equivalence checking Page Link: Formal equivalence checking - Posted By: computer science crazy Created at: Tuesday 24th of February 2009 03:22:34 AM | |||
Formal equivalence checking process is a part of electronic design automation (EDA), commonly used during the development of digital integrated circuits, to formally prove that two representations of a circuit design exhibit exactly the same behavior.In general, there is a wide range of possible definitions of functional equivalence covering comparisons between different levels of abstraction and varying granularity of timing details. | |||
Title: Formal Specification on Static Single Assignment Form Page Link: Formal Specification on Static Single Assignment Form - Posted By: nit_cal Created at: Friday 30th of October 2009 06:03:39 PM | |||
Abstract Static single-assignment is a form of program representation which is becoming increasingly popular because of its ease in handling optimizations. Transforming given code into SSA form results in a code for which data analysis is simpler as it is the inherent property of SSA form. Though there exists formal specifications for code on general form, the framework of dependency relations and formal specification specific to code in SSA form are not present in literature. In this thesis we have specified a framework for specifying transfor..............etc |
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