02-08-2016, 02:28 PM
— Digital visual interface transmitter and receiver in
a multimedia system allow for transmitting of high definition
video and audio data between the source and the receiver across
a serial page link at high speeds. This project highlights a detailed
development of digital visual interface (DVI) transmitter and
receiver in multimedia system. These include developing the
architecture DVI receiver and transmitter, high speed
serializer, clock and data recovery circuits and deserializer
through the efficient use of FPGA resources. The project makes
use of TMDS (Transition Minimized Differential Signaling)
technique, that involves advanced TMDS encoding and
decoding algorithms using DC balanced transmission, and helps
reducing EMI over the transmission lines.
The VHDL code for the encoder circuit is brought out
and verified for the values of the tabular column given and
the waveforms are obtained for the same as given in fig. This
TMDS encoder is a programmable logic component that
implements the 8b/10b encoding algorithm required by the
DVI and HDMI video interfaces.The conventional analog video graphics array (VGA)
standard has been replaced by the standard digital visual
interface (DVI) with the evolution of the display technology.
Digital multimedia interface made use of LVDS technology,
in the LVDS technology cable length was limited to short
distance. The proposed work makes use of TMDS technology
with TMDS encoding and decoding algorithms to overcome
the drawbacks of the LVDS technology
The digital visual interface (DVI) specification
provides a high speed digital connection for visual data types
that are display technology independently. The interface is
primarily focused at providing a connection between a
computer and its display device. The DVI transmitter and
receiver are connected through a single or dual TMDS serial
link. The TMDS page link is used to send graphics data to the
monitor. A TMDS page link consists of a single clock channel and
three data channels (RGB). The transitions minimization is
achieved by implementing advanced encoding algorithm on
each of the three channels, convert 8 bit of video or audio
data into a 10 bit transition minimized DC balanced
sequence. This advance coding algorithm enables robust
clock recovery and data recovery at the receiver. Thus, it
achieves greater skew tolerance for transmission over longer
cable length. In the TMDS standard the type of I/O logic,
which is CML (Current Mode Logic circuit), is also included
hence the name “TM” due to the encoder/decoder and “DS”
relates to the I/O circuit.
a multimedia system allow for transmitting of high definition
video and audio data between the source and the receiver across
a serial page link at high speeds. This project highlights a detailed
development of digital visual interface (DVI) transmitter and
receiver in multimedia system. These include developing the
architecture DVI receiver and transmitter, high speed
serializer, clock and data recovery circuits and deserializer
through the efficient use of FPGA resources. The project makes
use of TMDS (Transition Minimized Differential Signaling)
technique, that involves advanced TMDS encoding and
decoding algorithms using DC balanced transmission, and helps
reducing EMI over the transmission lines.
The VHDL code for the encoder circuit is brought out
and verified for the values of the tabular column given and
the waveforms are obtained for the same as given in fig. This
TMDS encoder is a programmable logic component that
implements the 8b/10b encoding algorithm required by the
DVI and HDMI video interfaces.The conventional analog video graphics array (VGA)
standard has been replaced by the standard digital visual
interface (DVI) with the evolution of the display technology.
Digital multimedia interface made use of LVDS technology,
in the LVDS technology cable length was limited to short
distance. The proposed work makes use of TMDS technology
with TMDS encoding and decoding algorithms to overcome
the drawbacks of the LVDS technology
The digital visual interface (DVI) specification
provides a high speed digital connection for visual data types
that are display technology independently. The interface is
primarily focused at providing a connection between a
computer and its display device. The DVI transmitter and
receiver are connected through a single or dual TMDS serial
link. The TMDS page link is used to send graphics data to the
monitor. A TMDS page link consists of a single clock channel and
three data channels (RGB). The transitions minimization is
achieved by implementing advanced encoding algorithm on
each of the three channels, convert 8 bit of video or audio
data into a 10 bit transition minimized DC balanced
sequence. This advance coding algorithm enables robust
clock recovery and data recovery at the receiver. Thus, it
achieves greater skew tolerance for transmission over longer
cable length. In the TMDS standard the type of I/O logic,
which is CML (Current Mode Logic circuit), is also included
hence the name “TM” due to the encoder/decoder and “DS”
relates to the I/O circuit.
