24-08-2011, 11:05 AM
[attachment=15420]
Features :
• Zero Capacitor DRAM
• No capacitor in its memory cell
• Capacitance is stored in FB of SOI wafer itself
• Cell consists of a single transistor
Structure of memory cell:
Single MOS transistor
Merits
• High Data Retention time
#Due to large amount charge
• High Read/Write speed
#Approx 3nS
• Consumes very low Power
• Highly Scalable
#Size of Test chips
~1st 90nm
~Finally 35nm
• Low cost
#Reduces total Die Area
• Manufacturing is simple
Features :
• Zero Capacitor DRAM
• No capacitor in its memory cell
• Capacitance is stored in FB of SOI wafer itself
• Cell consists of a single transistor
Structure of memory cell:
Single MOS transistor
Merits
• High Data Retention time
#Due to large amount charge
• High Read/Write speed
#Approx 3nS
• Consumes very low Power
• Highly Scalable
#Size of Test chips
~1st 90nm
~Finally 35nm
• Low cost
#Reduces total Die Area
• Manufacturing is simple
