26-01-2010, 11:26 PM
a. VLSI IMPLEMENTATION OF AN EDGE-ORIENTED
b. IMAGE SCALING PROCESSOR
c. RTL DESIGN AND SIMULATION OF MICRO CONTROLLER IN HDL
d. HDL IMPLEMENTATION OF ERROR DETECTION AND CORRECTION CIRCUIT
e. AUTOMATIC VERIFICATION STIMULUS GENERATION FOR INTERFACE PROTOCOLS A PARALLEL PRUNED BIT-REVERSAL INTERLEAVER
f. A VLIW VECTOR MEDIA COPROCESSOR WITH CASCADED SIMD ALUS
g. FLEXIBLE HARDWARE PROCESSOR FOR ELLIPTIC CURVE CRYPTOGRAPHY OVER NIST PR
h. IME FIELDS
i. FLEXILICON ARCHITECTURE AND ITS VLSI IMPLEMENTATION
j. MULTIPLICATION ACCELERATION THROUGH TWIN PRECISION
k. ON THE EXPLOITATION OF NARROW-WIDTH VALUES FOR IMPROVING REGISTER FILE RELIABILITY
l. REALIZING A SUB-LINEAR TIME STRING-MATCHING ALGORITHM WITH A HARDWARE ACCELERATOR USING BLOOM FILTERS
m. FAST ENHANCEMENT OF VALIDATION TEST SETS FOR IMPROVING THE STUCK-AT FAULT COVERAGE OF RTL CIRCUITS
n. TIME-EFFICIENT SINGLE CONSTANT MULTIPLICATION BASED ON OVERLAPPING DIGIT PATTERNS
o. HIGH PERFORMANCE, ENERGY EFFICIENCY, AND SCALABILITY WITH GALS CHIP MULTIPROCESSORS
p. FPGA IMPLEMENTATION OF SUPPORT VECTOR MACHINE BASED ISOLATED DIGIT RECOGNITION SYSTEM
q. FPGA IMPLEMENTATION OF THE TERNARY PULSE COMPRESSION SEQUENCES WITH GOOD DISCRIMINATION FACTOR VALUES.
r. HIGH PERFORMANCE, ENERGY EFFICIENCY, AND SCALABILITY WITH GALS CHIP MULTIPROCESSORS
s. A NOVEL CARRY-LOOK AHEAD APPROACH TO AN UNIFIED BCD AND BINARY ADDER/SUBTRACTOR
t. HIGHER RADIX AND REDUNDANCY FACTOR FOR FLOATING POINT SRT DIVISION USING VHDL / VERILOG
u. AREA-EFFICIENT ARITHMETIC EXPRESSION EVALUATION USING DEEPLY PIPELINED FLOATING POINT CORES USING VHDL
v. IMPROVING ERROR TOLERANCE FOR MULTITHREADED
w. REGISTER FILES
x. NOVEL BCD ADDERS AND THEIR REVERSIBLE LOGIC IMPLEMENTATION FOR IEEE 754R FORMAT
y. HIGH SPEED RECURSION ARCHITECTURE FOR MAP- BASED TURBO DECODERS
z. CONCURRENT ERROR DETECTION IN REED SOLOMON ENCODERS AND DECODERS
aa. MODELED WITH NON-DETERMINISTIC EXTENDED FSM
bb. FPGA IMPLEMENTATION OF THE TERNARY PULSE COMPRESSION SEQUENCES WITH GOOD DISCRIMINATION FACTOR VALUES.
cc. A FULLY PIPELINED ARCHITECTURE FOR THE LOCO-I COMPRESSION ALGORITHM
dd. FPGA IMPLEMENTATION OF A MULTI-RATE PUNCTURED VITERBI DECODER COMPATIBLE WITH THE DVB-T STANDARD
ee. FPGA IMPLEMENTATION OF SUPPORT VECTOR MACHINE BASED ISOLATED DIGIT RECOGNITION SYSTEM
ff. A FULLY PIPELINED ARCHITECTURE FOR THE LOCO-I
gg. COMPRESSION ALGORITHM
hh. MULTI-GB/S LDPC CODE DESIGN AND IMPLEMENTATION
ii. DESIGN AND IMPLEMENTATION OF AES USING VHDL
jj. COST-EFFICIENT SHA HARDWARE ACCELERATORS
kk. EFFECTIVE USES OF FPGAS FOR BRUTE-FORCE ATTACK ON RC4 CIPHERS
ll. FPGA IMPLEMENTATION(S) OF A SCALABLE ENCRYPTION ALGORITHM USING VHDL
mm. A ROBUST UART ARCHITECTURE BASED ON RECURSIVE RUNNING SUM FILTER FOR BETTER NOISE PERFORMANCE
nn. COMPACT HARDWAE DESIGN OF WHIRLPOOL HASHING CORE
oo. ENERGY-EFFICIENT DYNAMIC INSTRUCTION SCHEDULING LOGIC THROUGH INSTRUCTION GROUPING
pp. LOW POWER RECONFIGURATION TECHNIQUE FOR COARSE-GRAINED RECONFIGURABLE ARCHITECTURE
qq. POWER REDUCTION OF ASYNCHRONOUS LOGIC CIRCUITS USING ACTIVITY DETECTION
rr. TAG OVERFLOW BUFFERING: REDUCING TOTAL MEMORY ENERGY BY REDUCED-TAG MATCHING
ss. A LOW POWER JPEG2000 ENCODER WITH ITERATIVE AND FAULT TOLERANT ERROR CONCEALMENT
tt. DESIGN OPTIMIZATION OF TIME- AND COST-CONSTRAINED FAULT-TOLERANT EMBEDDED SYSTEMS WITH CHECKPOINTING AND REPLICATION
uu. LOW POWER DESIGN OF PRECOMPUTATION-BASED CONTENT-ADDRESSABLE MEMORY USING VHDL / VERILOG
vv. L-CBF: A LOW-POWER, FAST COUNTING BLOOM FILTER ARCHITECTURE USING VHDL
ww. LOW-POWER LEADING-ZERO COUNTING AND ANTICIPATION LOGIC FOR HIGH-SPEED FLOATING POINT UNITS
xx. FPGA IMPLEMENTATION OF LOW POWER PARALLEL MULTIPLIER
yy. A LOW POWER JPEG2000 ENCODER WITH ITERATIVE AND FAULT TOLERANT ERROR CONCEALMENT
zz. VLSI ARCHITECTURES OF PERCEPTUAL BASED VIDEO WATERMARKING FOR REAL-TIME COPYRIGHT PROTECTION
aaa. LOW POWER HARDWARE ARCHITECTURE FOR VBSME USING PIXEL TRUNCATION USING VHDL
bbb. A MODELING OF A DYNAMICALLY RECONFIGURABLE PROCESSOR USING VHDL
ccc. DIGITAL DESIGN OF DS-CDMA TRANSMITTER DESIGN USING VHDL AND FPGA
ddd. FPGA IMPLEMENTATION OF ADAPTIVE IIR FILTERS WITH PARTICLE SWARM OPTIMIZATION ALGORITHM
eee. FPGA IMPLEMENTATION OF LOW POWER PARRALLEL MULTIPLIER
fff. FPGA BASED CUSTOMIZABLE SYSTOLIC ARCHITECTURE
ggg. FOR IMAGE PROCESSING APPLICATIONS
b. IMAGE SCALING PROCESSOR
c. RTL DESIGN AND SIMULATION OF MICRO CONTROLLER IN HDL
d. HDL IMPLEMENTATION OF ERROR DETECTION AND CORRECTION CIRCUIT
e. AUTOMATIC VERIFICATION STIMULUS GENERATION FOR INTERFACE PROTOCOLS A PARALLEL PRUNED BIT-REVERSAL INTERLEAVER
f. A VLIW VECTOR MEDIA COPROCESSOR WITH CASCADED SIMD ALUS
g. FLEXIBLE HARDWARE PROCESSOR FOR ELLIPTIC CURVE CRYPTOGRAPHY OVER NIST PR
h. IME FIELDS
i. FLEXILICON ARCHITECTURE AND ITS VLSI IMPLEMENTATION
j. MULTIPLICATION ACCELERATION THROUGH TWIN PRECISION
k. ON THE EXPLOITATION OF NARROW-WIDTH VALUES FOR IMPROVING REGISTER FILE RELIABILITY
l. REALIZING A SUB-LINEAR TIME STRING-MATCHING ALGORITHM WITH A HARDWARE ACCELERATOR USING BLOOM FILTERS
m. FAST ENHANCEMENT OF VALIDATION TEST SETS FOR IMPROVING THE STUCK-AT FAULT COVERAGE OF RTL CIRCUITS
n. TIME-EFFICIENT SINGLE CONSTANT MULTIPLICATION BASED ON OVERLAPPING DIGIT PATTERNS
o. HIGH PERFORMANCE, ENERGY EFFICIENCY, AND SCALABILITY WITH GALS CHIP MULTIPROCESSORS
p. FPGA IMPLEMENTATION OF SUPPORT VECTOR MACHINE BASED ISOLATED DIGIT RECOGNITION SYSTEM
q. FPGA IMPLEMENTATION OF THE TERNARY PULSE COMPRESSION SEQUENCES WITH GOOD DISCRIMINATION FACTOR VALUES.
r. HIGH PERFORMANCE, ENERGY EFFICIENCY, AND SCALABILITY WITH GALS CHIP MULTIPROCESSORS
s. A NOVEL CARRY-LOOK AHEAD APPROACH TO AN UNIFIED BCD AND BINARY ADDER/SUBTRACTOR
t. HIGHER RADIX AND REDUNDANCY FACTOR FOR FLOATING POINT SRT DIVISION USING VHDL / VERILOG
u. AREA-EFFICIENT ARITHMETIC EXPRESSION EVALUATION USING DEEPLY PIPELINED FLOATING POINT CORES USING VHDL
v. IMPROVING ERROR TOLERANCE FOR MULTITHREADED
w. REGISTER FILES
x. NOVEL BCD ADDERS AND THEIR REVERSIBLE LOGIC IMPLEMENTATION FOR IEEE 754R FORMAT
y. HIGH SPEED RECURSION ARCHITECTURE FOR MAP- BASED TURBO DECODERS
z. CONCURRENT ERROR DETECTION IN REED SOLOMON ENCODERS AND DECODERS
aa. MODELED WITH NON-DETERMINISTIC EXTENDED FSM
bb. FPGA IMPLEMENTATION OF THE TERNARY PULSE COMPRESSION SEQUENCES WITH GOOD DISCRIMINATION FACTOR VALUES.
cc. A FULLY PIPELINED ARCHITECTURE FOR THE LOCO-I COMPRESSION ALGORITHM
dd. FPGA IMPLEMENTATION OF A MULTI-RATE PUNCTURED VITERBI DECODER COMPATIBLE WITH THE DVB-T STANDARD
ee. FPGA IMPLEMENTATION OF SUPPORT VECTOR MACHINE BASED ISOLATED DIGIT RECOGNITION SYSTEM
ff. A FULLY PIPELINED ARCHITECTURE FOR THE LOCO-I
gg. COMPRESSION ALGORITHM
hh. MULTI-GB/S LDPC CODE DESIGN AND IMPLEMENTATION
ii. DESIGN AND IMPLEMENTATION OF AES USING VHDL
jj. COST-EFFICIENT SHA HARDWARE ACCELERATORS
kk. EFFECTIVE USES OF FPGAS FOR BRUTE-FORCE ATTACK ON RC4 CIPHERS
ll. FPGA IMPLEMENTATION(S) OF A SCALABLE ENCRYPTION ALGORITHM USING VHDL
mm. A ROBUST UART ARCHITECTURE BASED ON RECURSIVE RUNNING SUM FILTER FOR BETTER NOISE PERFORMANCE
nn. COMPACT HARDWAE DESIGN OF WHIRLPOOL HASHING CORE
oo. ENERGY-EFFICIENT DYNAMIC INSTRUCTION SCHEDULING LOGIC THROUGH INSTRUCTION GROUPING
pp. LOW POWER RECONFIGURATION TECHNIQUE FOR COARSE-GRAINED RECONFIGURABLE ARCHITECTURE
qq. POWER REDUCTION OF ASYNCHRONOUS LOGIC CIRCUITS USING ACTIVITY DETECTION
rr. TAG OVERFLOW BUFFERING: REDUCING TOTAL MEMORY ENERGY BY REDUCED-TAG MATCHING
ss. A LOW POWER JPEG2000 ENCODER WITH ITERATIVE AND FAULT TOLERANT ERROR CONCEALMENT
tt. DESIGN OPTIMIZATION OF TIME- AND COST-CONSTRAINED FAULT-TOLERANT EMBEDDED SYSTEMS WITH CHECKPOINTING AND REPLICATION
uu. LOW POWER DESIGN OF PRECOMPUTATION-BASED CONTENT-ADDRESSABLE MEMORY USING VHDL / VERILOG
vv. L-CBF: A LOW-POWER, FAST COUNTING BLOOM FILTER ARCHITECTURE USING VHDL
ww. LOW-POWER LEADING-ZERO COUNTING AND ANTICIPATION LOGIC FOR HIGH-SPEED FLOATING POINT UNITS
xx. FPGA IMPLEMENTATION OF LOW POWER PARALLEL MULTIPLIER
yy. A LOW POWER JPEG2000 ENCODER WITH ITERATIVE AND FAULT TOLERANT ERROR CONCEALMENT
zz. VLSI ARCHITECTURES OF PERCEPTUAL BASED VIDEO WATERMARKING FOR REAL-TIME COPYRIGHT PROTECTION
aaa. LOW POWER HARDWARE ARCHITECTURE FOR VBSME USING PIXEL TRUNCATION USING VHDL
bbb. A MODELING OF A DYNAMICALLY RECONFIGURABLE PROCESSOR USING VHDL
ccc. DIGITAL DESIGN OF DS-CDMA TRANSMITTER DESIGN USING VHDL AND FPGA
ddd. FPGA IMPLEMENTATION OF ADAPTIVE IIR FILTERS WITH PARTICLE SWARM OPTIMIZATION ALGORITHM
eee. FPGA IMPLEMENTATION OF LOW POWER PARRALLEL MULTIPLIER
fff. FPGA BASED CUSTOMIZABLE SYSTOLIC ARCHITECTURE
ggg. FOR IMAGE PROCESSING APPLICATIONS