01-10-2009, 06:48 AM
VLSI BASED PROJECTS
=>On VLSI design of rank order filtering using DCRAM architecture (IEEE 2007)
=>A BIST circuit for DLL fault detection (IEEE 2008)
=>Low power leading zero counting and anticipation logic for high speed floating point unit (IEEE 2008)
=>Effective uses of FPGAS for brute force attack on RC4 ciphers (IEEE 2008)
=>Efficient communication between the embedded processor and the reconfigurable logic on an FPGA (IEEE 2008)
=>Hybrid type cam design for both power and performance efficiency (IEEE 2008)
=>Robust concurrent online testing of network on chip based on SOCS (IEEE 2008)
=>An accumulator based compaction scheme for online BIST of RAMS (IEEE 2008)
=>The reconfigurable instruction call array (IEEE 2008)
=>A medium-grain reconfigurable for DSP VLSI design, benchmark mapping and performance (IEEE 2008)
=>Area-efficient arithmetic expression evaluation using deeply pipelined floating-point cores (IEEE 2008)
=>FPGA implementation of scalable encryption algorithm (IEEE 2008)
=>Low power design of precomputation based content addressable memory (IEEE 2008)
=>Automatic constraint based test generation for behavioral HDL models (IEEE 2008)
=>Higher radix and redundancy factor for floating point SRT division (IEEE 2008)
=>Automatic design of reconfigurable domain-specific flexible cores (IEEE 2008)
=>Enhancement of fault injection techniques based on the modification of VHDL code (IEEE 2008)
=> Diagnosis framework for locating failed segment of path delay faults (IEEE 2008)
=>LFSR reseeding scheme achieving low power dissipation during test (IEEE 2008)
=>Registers for phase difference based logic (IEEE 2007)
=>A combined gate replacement and input vector control approach for leakage current reduction (IEEE 2006)
=>A high efficiency fully synchronous buck converter power delivery system based on finite state machine (IEEE 2006)
=>X-masking during logic BIST and impact on defect coverage (IEEE 2006)
=>New techniques for attestable fault identification in sequential circuits (IEEE 2006)
=>New and improved BIST diagnosis method combinatorial group testing theory (IEEE 2006)
=>Energy management for battery power reconfigurable computing platforms (IEEE 2006)
=>Design specific path delay testing in lookup table based FPGA (IEEE 2006)
=>Weighted pseudo- random hybrid BIST (IEEE 2004)
=>Low-power scan design using first level supply gating (IEEE 2005)
=>Optimization techniques for FPGA based wave pipelined DSP blocks (IEEE 2005)
=>A source synchronous double data rate parallel optical transciever ic (IEEE 2005)
=>Double sampling data checking technique an online testing solution for multi source noise induced errors on chip interconnects and buses (IEEE 2004)
=>Leakage current reduction in CMOS circuit using ip vector control(IEEE 2004)
=>Improving linear test data compression (IEEE 2006)
=>Exact and heuristic approaches to input vector control for leakage power reduction (IEEE 2006)
=>Auto scan : A scan design without external scan input or output (IEEE 2005)
=>Characterization, Test and logic synthesis of Andor-Invertor (AOI)(IEEE 2005)
=>Diagnosis of logic circuits using compressed deterministic data and on chip response comparison (IEEE 2006)
=>Extraction error modeling and automated model debugging in high performance custom design(IEEE 2006)
=>Pipelined array based fir filter folding(IEEE 2005)
=>Space vector modulation using VLSI(IEEE 2002)
=>Variable run length coding for embedded progressive wavelet based image compression and decompression
=>Hardware implementation of finger printing algorithm suited for digital cinema
=>Finger printing reorganization
=>Speed Referencing for continues hot rolling mill
=>digital audio stenography
=>Multi input and multi out for wireless communication system
=>VLSI based traffic light controller
=>A general purpose cell sequencer / Scheduler for ATM switches
=>Wireless home appliances controller
=>Speed control of DC motor
=>Stepper motor controller
=>Wireless camera controller
=>Event driven simulation of VLSI circuits
=>A low-power multiplier with the spurious power suppression technique (IEEE 2007)
=>Go/no- go testing of VCO modulation RF transceivers through the delayed-RF setup(IEEE 2007)
=>A BIST TPG for low power dissipation and high fault coverage(IEEE 2007)
=>Universal VLSI based on a redundant multiple valued sequential logic operation(IEEE 2007)
=>A VHDL implementation of UART design with BIST capability(MALAYSAN JOURNAL 2006)
=>Advanced encryption slandered (AES)
=>High speed VLSI architecture for parallel reed Solomon decoder
=>On VLSI design of rank order filtering using DCRAM architecture (IEEE 2007)
=>A BIST circuit for DLL fault detection (IEEE 2008)
=>Low power leading zero counting and anticipation logic for high speed floating point unit (IEEE 2008)
=>Effective uses of FPGAS for brute force attack on RC4 ciphers (IEEE 2008)
=>Efficient communication between the embedded processor and the reconfigurable logic on an FPGA (IEEE 2008)
=>Hybrid type cam design for both power and performance efficiency (IEEE 2008)
=>Robust concurrent online testing of network on chip based on SOCS (IEEE 2008)
=>An accumulator based compaction scheme for online BIST of RAMS (IEEE 2008)
=>The reconfigurable instruction call array (IEEE 2008)
=>A medium-grain reconfigurable for DSP VLSI design, benchmark mapping and performance (IEEE 2008)
=>Area-efficient arithmetic expression evaluation using deeply pipelined floating-point cores (IEEE 2008)
=>FPGA implementation of scalable encryption algorithm (IEEE 2008)
=>Low power design of precomputation based content addressable memory (IEEE 2008)
=>Automatic constraint based test generation for behavioral HDL models (IEEE 2008)
=>Higher radix and redundancy factor for floating point SRT division (IEEE 2008)
=>Automatic design of reconfigurable domain-specific flexible cores (IEEE 2008)
=>Enhancement of fault injection techniques based on the modification of VHDL code (IEEE 2008)
=> Diagnosis framework for locating failed segment of path delay faults (IEEE 2008)
=>LFSR reseeding scheme achieving low power dissipation during test (IEEE 2008)
=>Registers for phase difference based logic (IEEE 2007)
=>A combined gate replacement and input vector control approach for leakage current reduction (IEEE 2006)
=>A high efficiency fully synchronous buck converter power delivery system based on finite state machine (IEEE 2006)
=>X-masking during logic BIST and impact on defect coverage (IEEE 2006)
=>New techniques for attestable fault identification in sequential circuits (IEEE 2006)
=>New and improved BIST diagnosis method combinatorial group testing theory (IEEE 2006)
=>Energy management for battery power reconfigurable computing platforms (IEEE 2006)
=>Design specific path delay testing in lookup table based FPGA (IEEE 2006)
=>Weighted pseudo- random hybrid BIST (IEEE 2004)
=>Low-power scan design using first level supply gating (IEEE 2005)
=>Optimization techniques for FPGA based wave pipelined DSP blocks (IEEE 2005)
=>A source synchronous double data rate parallel optical transciever ic (IEEE 2005)
=>Double sampling data checking technique an online testing solution for multi source noise induced errors on chip interconnects and buses (IEEE 2004)
=>Leakage current reduction in CMOS circuit using ip vector control(IEEE 2004)
=>Improving linear test data compression (IEEE 2006)
=>Exact and heuristic approaches to input vector control for leakage power reduction (IEEE 2006)
=>Auto scan : A scan design without external scan input or output (IEEE 2005)
=>Characterization, Test and logic synthesis of Andor-Invertor (AOI)(IEEE 2005)
=>Diagnosis of logic circuits using compressed deterministic data and on chip response comparison (IEEE 2006)
=>Extraction error modeling and automated model debugging in high performance custom design(IEEE 2006)
=>Pipelined array based fir filter folding(IEEE 2005)
=>Space vector modulation using VLSI(IEEE 2002)
=>Variable run length coding for embedded progressive wavelet based image compression and decompression
=>Hardware implementation of finger printing algorithm suited for digital cinema
=>Finger printing reorganization
=>Speed Referencing for continues hot rolling mill
=>digital audio stenography
=>Multi input and multi out for wireless communication system
=>VLSI based traffic light controller
=>A general purpose cell sequencer / Scheduler for ATM switches
=>Wireless home appliances controller
=>Speed control of DC motor
=>Stepper motor controller
=>Wireless camera controller
=>Event driven simulation of VLSI circuits
=>A low-power multiplier with the spurious power suppression technique (IEEE 2007)
=>Go/no- go testing of VCO modulation RF transceivers through the delayed-RF setup(IEEE 2007)
=>A BIST TPG for low power dissipation and high fault coverage(IEEE 2007)
=>Universal VLSI based on a redundant multiple valued sequential logic operation(IEEE 2007)
=>A VHDL implementation of UART design with BIST capability(MALAYSAN JOURNAL 2006)
=>Advanced encryption slandered (AES)
=>High speed VLSI architecture for parallel reed Solomon decoder