14-05-2011, 11:01 AM
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2. THEORY
Multi-gate FET, e.g. FinFET devices are the most promising contenders to replace bulk FETs in sub- 45 nm CMOS technologies due to their improved sub threshold and short channel behavior, associated with low leakage currents. The introduction of novel gate stack materials (e.g. metal gate, high-k dielectric) and modified device architectures (e.g. fully depleted, undoped fins) affect the analog device properties significantly. First measurements indicate enhanced intrinsic gain (gm/gDS) and promising matching behavior of FinFETs. The resulting benefits regarding the speed-accuracy-power trade-off in analog circuit design will be shown in this work. Additionally novel device specific effects will be discussed. The hysteresis effect caused by charge trapping in high-k dielectrics or self-heating due to the high thermal resistor of the BOX isolation are possible challenges for analog design in these emerging technologies.
To gain an early assessment of the impact of such parasitic effects SPICE based models are derived and applied in analog building blocks.
2.1 FinFET structure and layout
• The double-gate FinFET—a promising candidate to continue CMOS scaling deep into the nanometer regime
• Gate straddles thin silicon fin, forming two conducting channels on sidewalls
3.1 3D view of FinFET
2.2 Layout similar to bulk-Si MOSFET
Fig. 2.2 Bulk-Si MOSFET
Fig. 2.3 Multi-fin layout
Source (all images): T-J King, et al, “FinFET Technology Optimization…”
2.3 FinFET modeling approach
• Need a suitable SPICE model for initial design based on transistor I-V and high-frequency AC characteristics
• Modeling approaches
• Small-signal equivalent model
• Uses simple lumped circuit elements
• Suitable for only selected bias points
• Avoids need for complete device model
• Valid only for small-signal operation
• Subcircuit model (adapt 60-GHz CMOS approach)
• Begin with core BSIMSOI model
• Extend core subcircuit with extrinsic parasitics (BSIMSOI3.1 already includes gate resistance model)
• DC I-V curve fitting to extract core BSIM parameters
• Small-signal Y-parameter fitting to extract parasitic component values
• Also suitable for large-signal simulation
[attachment=13887]
[attachment=13888]
[attachment=13889]
[attachment=13890]
[attachment=13891]
2. THEORY
Multi-gate FET, e.g. FinFET devices are the most promising contenders to replace bulk FETs in sub- 45 nm CMOS technologies due to their improved sub threshold and short channel behavior, associated with low leakage currents. The introduction of novel gate stack materials (e.g. metal gate, high-k dielectric) and modified device architectures (e.g. fully depleted, undoped fins) affect the analog device properties significantly. First measurements indicate enhanced intrinsic gain (gm/gDS) and promising matching behavior of FinFETs. The resulting benefits regarding the speed-accuracy-power trade-off in analog circuit design will be shown in this work. Additionally novel device specific effects will be discussed. The hysteresis effect caused by charge trapping in high-k dielectrics or self-heating due to the high thermal resistor of the BOX isolation are possible challenges for analog design in these emerging technologies.
To gain an early assessment of the impact of such parasitic effects SPICE based models are derived and applied in analog building blocks.
2.1 FinFET structure and layout
• The double-gate FinFET—a promising candidate to continue CMOS scaling deep into the nanometer regime
• Gate straddles thin silicon fin, forming two conducting channels on sidewalls
3.1 3D view of FinFET
2.2 Layout similar to bulk-Si MOSFET
Fig. 2.2 Bulk-Si MOSFET
Fig. 2.3 Multi-fin layout
Source (all images): T-J King, et al, “FinFET Technology Optimization…”
2.3 FinFET modeling approach
• Need a suitable SPICE model for initial design based on transistor I-V and high-frequency AC characteristics
• Modeling approaches
• Small-signal equivalent model
• Uses simple lumped circuit elements
• Suitable for only selected bias points
• Avoids need for complete device model
• Valid only for small-signal operation
• Subcircuit model (adapt 60-GHz CMOS approach)
• Begin with core BSIMSOI model
• Extend core subcircuit with extrinsic parasitics (BSIMSOI3.1 already includes gate resistance model)
• DC I-V curve fitting to extract core BSIM parameters
• Small-signal Y-parameter fitting to extract parasitic component values
• Also suitable for large-signal simulation
