21-03-2011, 12:07 PM
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Single Port CAM
Content Addressable Memory is a memory which its locations are accessed through comparing Tags rather than providing their addresses. Each stored data is associated with a unique tag. When we like to retrieve the data, we apply its tag with a read signal to all locations simultaneously. The applied tag is compared with all stored tags simultaneously. If any of the stored tags matches the applied tag, the equality signal of the location comparator enables the output of the location, and the data is placed on the data bus in order to be read by the processor. Figure 1 depicts a single port CAM.
Dual Port CAM
In a multiprocessor interconnection network architecture proposed by Dr. Ayyad, the need arises for implementing CAM cache memory modules at the cross-point of the crossbar switch, through which the processors exchange the variables. The source processor can write the variable to a selected set of cross-point CAM modules simultaneously, and can search for a variable in the set of CAMs connected to its input bus simultaneously. So, we need a dual port CAM like the one shown in figure 2. Through the left (Write port), one processor can write a variable to the first available memory location. The written variable includes the data (the value of the variable) and an associated tag stored in the tag field of the memory location. Another processor can search in the CAM for the variable by applying the tag to the tag field and a read signal through the right port (the read port). The tag will be compared to the stored tags in all location simultaneously, and, if a match occurs, the equality signal of the comparator will enable the output of the data field to output the data on the output data bus [O31-O0].
The control circuit of the CAM includes a pointer circuit which points to the first available memory location for writing. When the system is reset, this pointer points to the first memory location. After writing to the current location, the pointer points to the next location, and so on. In the case of simultaneous write and read process, the circuit gives the priority for writing and gives the reading processor a WAIT signal. The WAIT signal can be obtained by ORing the active low RD and WR signal coming from the writing and the reading processors. The WAIT signal also, separates the tag bus of the reading processor by disabling the tri-state buffer Tr
Single Port CAM
Content Addressable Memory is a memory which its locations are accessed through comparing Tags rather than providing their addresses. Each stored data is associated with a unique tag. When we like to retrieve the data, we apply its tag with a read signal to all locations simultaneously. The applied tag is compared with all stored tags simultaneously. If any of the stored tags matches the applied tag, the equality signal of the location comparator enables the output of the location, and the data is placed on the data bus in order to be read by the processor. Figure 1 depicts a single port CAM.
Dual Port CAM
In a multiprocessor interconnection network architecture proposed by Dr. Ayyad, the need arises for implementing CAM cache memory modules at the cross-point of the crossbar switch, through which the processors exchange the variables. The source processor can write the variable to a selected set of cross-point CAM modules simultaneously, and can search for a variable in the set of CAMs connected to its input bus simultaneously. So, we need a dual port CAM like the one shown in figure 2. Through the left (Write port), one processor can write a variable to the first available memory location. The written variable includes the data (the value of the variable) and an associated tag stored in the tag field of the memory location. Another processor can search in the CAM for the variable by applying the tag to the tag field and a read signal through the right port (the read port). The tag will be compared to the stored tags in all location simultaneously, and, if a match occurs, the equality signal of the comparator will enable the output of the data field to output the data on the output data bus [O31-O0].
The control circuit of the CAM includes a pointer circuit which points to the first available memory location for writing. When the system is reset, this pointer points to the first memory location. After writing to the current location, the pointer points to the next location, and so on. In the case of simultaneous write and read process, the circuit gives the priority for writing and gives the reading processor a WAIT signal. The WAIT signal can be obtained by ORing the active low RD and WR signal coming from the writing and the reading processors. The WAIT signal also, separates the tag bus of the reading processor by disabling the tri-state buffer Tr
