16-03-2011, 10:23 AM
presented by:
B.SEETHALAKSHMI
[attachment=10274]
ABSTRACT
Chameleon chips are chips whose circuitry can be tailored specifically for the problem at hand. Chameleon chips would be an extension of what can already be done with field-programmable gate arrays (FPGAS). An FPGA is covered with a grid of wires. At each crossover, there's a switch that can be semipermanently opened or closed by sending it a special signal. Usually the chip must first be inserted in a little box that sends the programming signals. But now, labs in Europe, Japan, and the U.S. are developing techniques to rewire FPGA-like chips anytime--and even software that can map out circuitry that's optimized for specific problems.
The chips still won't change colors. But they may well color the way we use computers in years to come. It is a fusion between custom integrated circuits and programmable logic.In the case when we are doing highly performance oriented tasks custom chips that do one or two things spectacularly rather than lot of things averagely is used. Now using field programmed chips we have chips that can be rewired in an instant. Thus the benefits of customization can be brought to the mass market.
INTRODUCTION
Today's microprocessors sport a general-purpose design which has its own advantages and disadvantages.
Adv: One chip can run a range of programs. That's why you don't need separate computers for different jobs, such as crunching spreadsheets or editing digital photos
Disadv: For any one application, much of the chip's circuitry isn't needed, and the presence of those "wasted" circuits slows things down.
Suppose, instead, that the chip's circuits could be tailored specifically for the problem at hand--say, computer-aided design--and then rewired, on the fly, when you loaded a tax-preparation program. One set of chips, little bigger than a credit card, could do almost anything, even changing into a wireless phone. The market for such versatile marvels would be huge, and would translate into lower costs for users.
So computer scientists are hatching a novel concept that could increase number-crunching power--and trim costs as well. Call it the chameleon chip.
CHALLENGES FACED
Designers of multimedia systems face three significant challenges in today's ultra-competitive marketplace:
٭ Our products must do more,
٭ cost less, and
٭ be brought to the market quicker than ever.
ATTAINING THESE GOALS
Though each of these goals is individually attainable, the hat trick is generally unachievable with traditional design and implementation techniques. Fortunately, some new techniques are emerging from the study of reconfigurable computing that make it possible to design systems that satisfy all three requirements simultaneously.
DEVELOPING TECHNIQUES
But now, labs in Europe, Japan, and the U.S. are developing techniques to rewire FPGA-like chips anytime--and even software that can map out circuitry that's optimized for specific problems.
IMPROVED CHARACTERISTICS
In the case when we are doing highly performance oriented tasks custom chips that do one or two things spectacularly rather than lot of things averagely is used. Now using field programmed chips we have chips that can be rewired in an instant. Thus the benefits of customization can be brought to the mass market.
To be quick enough for personal information devices, the chips will need to completely reconfigure themselves in a millisecond or less. "That kind of chameleon device would be the killer app of reconfigurable computing" These experts predict that in the next couple of years reconfigurable systems will be used in cell phones to handle things like changes in telecommunications systems or standards as users travel between calling regions -- or between countries.
As it is getting more expensive and difficult to pattern, or etch, the elaborate circuitry used in microprocessors; many experts have predicted that maintaining the current rate of putting more circuits into ever smaller spaces will, sometime in the next 10 to 15 years, result in features on microchips no bigger than a few atoms, which would demand a nearly impossible level of precision in fabricating circuitry But reconfigurable chips don't need that type of precision and we can make computers that function at the nanoscale level
RECONFIGURING THE ARCHITECTURE
Some of the new configurable DSP architectures are reconfigurable too—that is, developers can modify their landscape on the fly, depending on the incoming data stream. This capability permits dynamic reconfigurability of the architecture as demanded by the application. Proponents of such chips are proclaiming an era of "chip-on-demand," wherein new algorithms can be accommodated on-chip in real time via software. This eliminates the cumbersome job of fitting the latest algorithms and protocols into existing rigid hardware. A reconfigurable communications processor (RCP) can reconfigured for different processing algorithms in one clock cycle.
Chameleon designers are revising the architecture to create a chip that can address a much broader range of applications. Plus, the supplier is preparing a new, more user-friendly suite of tools for traditional DSP designers. Thus, the company is dropping the term reconfigurability for the new architecture and going with a more traditional name, the streaming data processor (SDP).
Though the SDP will include a reconfigurable processing fabric, it will be substantially altered, the company says. Unlike the older RCP, the new chip won't have the ARM RISC core, and it will support a much higher clock rate. Additionally, it will be implemented in a 0.13-µm CMOS process to meet the signal processing needs of a much broader market.
RECONFIGURABLE COMPUTING:
History:
Although originally proposed in the late 1960s by a researcher at UCLA, reconfigurable computing is a relatively new field of study.
Present developments:
The decades-long delay had mostly to do with a lack of acceptable reconfigurable hardware. Reprogrammable logic chips like field programmable gate arrays (FPGAs) have been around for many years, but these chips have only recently reached gate densities making them suitable for high-end applications. (The densest of the current FPGAs have approximately 100,000 reprogrammable logic gates.) With an anticipated doubling of gate densities every 18 months, the situation will only become more favorable from this point forward.
Explanation:
Reconfigurable computing goes a step beyond programmable chips in the matter of flexibility. It is not only possible but relatively commonplace to "rewrite" the silicon so that it can perform new functions in a split second.
When we talk about reconfigurable computing we’re usually talking about FPGA-based system designs. Unfortunately, that doesn’t qualify the term precisely enough. System designers use FPGAs in many different ways. The most common use of an FPGA is for prototyping the design of an ASIC. In this scenario, the FPGA is present only on the prototype hardware and is replaced by the corresponding ASIC in the final production system. This use of FPGAs has nothing to do with reconfigurable computing.
However, many system designers are choosing to leave the FPGAs as part of the production hardware.
The logic within the FPGA can be changed if or when it is necessary, which has many advantages. For example, hardware bug fixes and upgrades can be administered as easily as their software counterparts. In order to support a new version of a network protocol, you can redesign the internal logic of the FPGA and send the enhancement to the affected customers by email. Once they’ve downloaded the new logic design to the system and restarted it, they’ll be able to use the new version of the protocol. This is configurable computing; reconfigurable computing goes one step further.
Reconfigurable computing involves manipulation of the logic within the FPGA at run-time. In other words, the design of the hardware may change in response to the demands placed upon the system while it is running. Here, the FPGA acts as an execution engine for a variety of different hardware functions — some executing in parallel, others in serial — much as a CPU acts as an execution engine for a variety of software threads. We might even go so far as to call the FPGA a reconfigurable processing unit (RPU).
Reconfigurable computing allows system designers to execute more hardware than they have gates to fit, which works especially well when there are parts of the hardware that are occasionally idle. One theoretical application is a smart cellular phone that supports multiple communication and data protocols, though just one a time. When the phone passes from a geographic region that is served by one protocol into a region that is served by another, the hardware is automatically reconfigured. This is reconfigurable computing at its best, and using this approach it is possible to design systems that do more, cost less, and have shorter design and implementation cycles.
Advantages:
Reconfigurable computing has several advantages.
First, it is possible to achieve greater functionality with a simpler hardware design. Because not all of the logic must be present in the FPGA at all times, the cost of supporting additional features is reduced to the cost of the memory required to store the logic design. Consider again the multiprotocol cellular phone. It would be possible to support as many protocols as could be fit into the available on-board ROM. It is even conceivable that new protocols could be uploaded from a base station to the handheld phone on an as-needed basis, thus requiring no additional memory.
The second advantage is lower system cost, which does not manifest itself exactly as you might expect. On a low-volume product, there will be some production cost savings, which result from the elimination of the expense of ASIC design and fabrication. However, for higher-volume products, the production cost of fixed hardware may actually be lower. We have to think in terms of lifetime system costs to see the savings. Systems based on reconfigurable computing are upgradable in the field. Such changes extend the useful life of the system, thus reducing lifetime costs.
The final advantage of reconfigurable computing is reduced time-to-market. The fact that you’re no longer using an ASIC is a big help in this respect. There are no chip design and prototyping cycles, which eliminates a large amount of development effort. In addition, the logic design remains flexible right up until (and even after) the product ships. This allows an incremental design flow, a luxury not typically available to hardware designers. You can even ship a product that meets the minimum requirements and add features after deployment. In the case of a networked product like a set-top box or cellular telephone, it may even be possible to make such enhancements without customer involvement.
RECONFIGURABLE PROCESSOR
A reconfigurable processor is a microprocessor with erasable hardware that can rewire itself dynamically. This allows the chip to adapt effectively to the programming tasks demanded by the particular software they are interfacing with at any given time. Ideally, the reconfigurable processor can transform itself from a video chip to a central processing unit (cpu) to a graphics chip, for example, all optimized to allow applications to run at the highest possible speed. The new chips can be called a "chip on demand." In practical terms, this ability can translate to immense flexibility in terms of device functions. For example, a single device could serve as both a camera and a tape recorder (among numerous other possibilities): you would simply download the desired software and the processor would reconfigure itself to optimize performance for that function.
We are developing an architecture and a prototype component that will combine a processor and a high performance reconfigurable array on a single chip. The reconfigurable array extends the usefulness and efficiency of the processor by providing the means to tailor its circuits for special tasks. The processor improves the efficiency of the reconfigurable array for irregular, general-purpose computation.
We anticipate that a processor combined with reconfigurable resources can achieve a significant performance improvement over either a separate processor or a separate reconfigurable device on an interesting range of problems drawn from embedded computing applications. As such, we hope to demonstrate that this composite device is an ideal system element for embedded processing.
Reconfigurable devices have proven extremely efficient for certain types of processing tasks. The key to their cost/performance advantage is that conventional processors are often limited by instruction bandwidth and execution restrictions or by an insufficient number or type of functional units. Reconfigurable logic exploits more program parallelism. By dedicating significantly less instruction memory per active computing element, reconfigurable devices achieve a 10x improvement in functional density over microprocessors. At the same time this lower memory ratio allows reconfigurable devices to deploy active capacity at a finer grained level, allowing them to realize a higher yield of their raw capacity, sometimes as much as 10x, than conventional processors.
The high functional density characteristic of reconfigurable devices comes at the expense of the high functional diversity characteristic of microprocessors. Microprocessors have evolved to a highly optimized configuration with clear cost/performance advantages over reconfigurable arrays for a large set of tasks with high functional diversity. By combining a reconfigurable array with a processing core we hope to achieve the best of both worlds.
While it is possible to combine a conventional processor with commercial reconfigurable devices at the circuit board level, integration radically changes the i/o costs and design point for both devices, resulting in a qualitatively different system. Notably, the lower on-chip communication costs allow efficient cooperation between the processor and array at a finer grain than is sensible with discrete designs.
RECONFIGURABLE CHIPS
Reconfigurable chips are simply the extreme end of programmability.
RECONFIGURABLE HARDWARE
Description:
For these reasons, chip designers are turning increasingly to reconfigurable hardware—integrated circuits where the architecture of the internal logic elements can be arranged and rearranged on the fly to fit particular applications.
In order to benefit from run-time reconfiguration, it is necessary that the FPGAs involved have some or all of the following features. The more of these features they have, the more flexible can be the system design. Deciding which hardware objects to execute and when Swapping hardware objects into and out of the reconfigurable logic Performing routing between hardware objects or between hardware objects and the hardware object framework. Of course, having software manage the reconfigurable hardware usually means having an embedded processor or microcontroller on-board. (We expect several vendors to introduce single-chip solutions that combine a CPU core and a block of reconfigurable logic by year’s end.) The embedded software that runs there is called the run-time environment and is analogous to the operating system that manages the execution of multiple software threads. Like threads, hardware objects may have priorities, deadlines, and contexts, etc. It is the job of the run-time environment to organize this information and make decisions based upon it.
The reason we need a run-time environment at all is that there are decisions to be made while the system is running. And as human designers, we are not available to make these decisions. So we impart these responsibilities to a piece of software. This allows us to write our application software at a very high level of abstraction.
Process:
To do this, the run-time environment must first locate space within the RPU that is large enough to execute the given hardware object. It must then perform the necessary routing between the hardware object’s inputs and outputs and the blocks of memory reserved for each data stream. Next, it must stop the appropriate clock, reprogram the internal logic, and restart the RPU. Once the object starts to execute, the run-time environment must continuously monitor the hardware object’s status flags to determine when it is done executing. Once it is done, the caller can be notified and given the results. The run-time environment is then free to reclaim the reconfigurable logic gates that were taken up by that hardware object and to wait for additional requests to arrive from the application software.
Benefits:
The principal benefits of reconfigurable computing are the ability to execute larger hardware designs with fewer gates and to realize the flexibility of a software-based solution while retaining the execution speed of a more traditional, hardware-based approach. This makes doing more with less a reality. In our own business we have seen tremendous cost savings, simply because our systems do not become obsolete as quickly as our competitors because reconfigurable computing enables the addition of new features in the field, allows rapid implementation of new standards and protocols on an as-needed basis, and protects their investment in computing hardware.
Whether you do it for your customers or for yourselves, you should at least consider using reconfigurable computing in your next design. You may find, as we have, that the benefits far exceed the initial learning curve. And as reconfigurable computing becomes more popular, these benefits will only increase.
ADVANTAGES OF RECONFIGURABILITY
Many system-on-a-chip (SoC) computer designs provide reconfigurability options that provide the high performance of hardware with the flexibility of software. To most designers, SoC means encapsulating one or more processing elements—that is, general-purpose embedded processors and/or digital signal processor (DSP) cores—along with memory, input/output devices, and other hardware into a single chip. These versatile chips can perform many different functions. However, while SoCs offer choices, the user can choose only among functions that already reside inside the device. Developers also create ASICs—chips that handle a limited set of tasks but do them very quickly.
The limitation of most types of complex hardware devices—SoCs, ASICs, and general-purpose cpus—is that the logical hardware functions cannot be modified once the silicon design is complete and fabricated. Consequently, developers are typically forced to amortize the cost of SoCs and ASICs over a product lifetime that may be extremely short in today's volatile technology environment.
Solutions involving combinations of cpus and FPGAs allow hardware functionality to be reprogrammed, even in deployed systems, and enable medical instrument OEMs to develop new platforms for applications that require rapid adaptation to input. The technologies combined provide the best of both worlds for system-level design. Careful analysis of computational requirements reveals that many algorithms are well suited to high-speed sequential processing, many can benefit from parallel processing capabilities, and many can be broken down into components that are split between the two. With this in mind, it makes sense to always use the best technology for the job at hand.
CURRENTLY AVAILABLE PROCESSORS
Reconfigurable processors are currently available from Chameleon Systems, Billions of Operations (BOPS), and PACT (Parallel Array Computing Technology).
Among those only Chameleon is providing a design environment, which allows customers to convert their algorithms to hardware configuration by themselves
B.SEETHALAKSHMI
[attachment=10274]
ABSTRACT
Chameleon chips are chips whose circuitry can be tailored specifically for the problem at hand. Chameleon chips would be an extension of what can already be done with field-programmable gate arrays (FPGAS). An FPGA is covered with a grid of wires. At each crossover, there's a switch that can be semipermanently opened or closed by sending it a special signal. Usually the chip must first be inserted in a little box that sends the programming signals. But now, labs in Europe, Japan, and the U.S. are developing techniques to rewire FPGA-like chips anytime--and even software that can map out circuitry that's optimized for specific problems.
The chips still won't change colors. But they may well color the way we use computers in years to come. It is a fusion between custom integrated circuits and programmable logic.In the case when we are doing highly performance oriented tasks custom chips that do one or two things spectacularly rather than lot of things averagely is used. Now using field programmed chips we have chips that can be rewired in an instant. Thus the benefits of customization can be brought to the mass market.
INTRODUCTION
Today's microprocessors sport a general-purpose design which has its own advantages and disadvantages.
Adv: One chip can run a range of programs. That's why you don't need separate computers for different jobs, such as crunching spreadsheets or editing digital photos
Disadv: For any one application, much of the chip's circuitry isn't needed, and the presence of those "wasted" circuits slows things down.
Suppose, instead, that the chip's circuits could be tailored specifically for the problem at hand--say, computer-aided design--and then rewired, on the fly, when you loaded a tax-preparation program. One set of chips, little bigger than a credit card, could do almost anything, even changing into a wireless phone. The market for such versatile marvels would be huge, and would translate into lower costs for users.
So computer scientists are hatching a novel concept that could increase number-crunching power--and trim costs as well. Call it the chameleon chip.
CHALLENGES FACED
Designers of multimedia systems face three significant challenges in today's ultra-competitive marketplace:
٭ Our products must do more,
٭ cost less, and
٭ be brought to the market quicker than ever.
ATTAINING THESE GOALS
Though each of these goals is individually attainable, the hat trick is generally unachievable with traditional design and implementation techniques. Fortunately, some new techniques are emerging from the study of reconfigurable computing that make it possible to design systems that satisfy all three requirements simultaneously.
DEVELOPING TECHNIQUES
But now, labs in Europe, Japan, and the U.S. are developing techniques to rewire FPGA-like chips anytime--and even software that can map out circuitry that's optimized for specific problems.
IMPROVED CHARACTERISTICS
In the case when we are doing highly performance oriented tasks custom chips that do one or two things spectacularly rather than lot of things averagely is used. Now using field programmed chips we have chips that can be rewired in an instant. Thus the benefits of customization can be brought to the mass market.
To be quick enough for personal information devices, the chips will need to completely reconfigure themselves in a millisecond or less. "That kind of chameleon device would be the killer app of reconfigurable computing" These experts predict that in the next couple of years reconfigurable systems will be used in cell phones to handle things like changes in telecommunications systems or standards as users travel between calling regions -- or between countries.
As it is getting more expensive and difficult to pattern, or etch, the elaborate circuitry used in microprocessors; many experts have predicted that maintaining the current rate of putting more circuits into ever smaller spaces will, sometime in the next 10 to 15 years, result in features on microchips no bigger than a few atoms, which would demand a nearly impossible level of precision in fabricating circuitry But reconfigurable chips don't need that type of precision and we can make computers that function at the nanoscale level
RECONFIGURING THE ARCHITECTURE
Some of the new configurable DSP architectures are reconfigurable too—that is, developers can modify their landscape on the fly, depending on the incoming data stream. This capability permits dynamic reconfigurability of the architecture as demanded by the application. Proponents of such chips are proclaiming an era of "chip-on-demand," wherein new algorithms can be accommodated on-chip in real time via software. This eliminates the cumbersome job of fitting the latest algorithms and protocols into existing rigid hardware. A reconfigurable communications processor (RCP) can reconfigured for different processing algorithms in one clock cycle.
Chameleon designers are revising the architecture to create a chip that can address a much broader range of applications. Plus, the supplier is preparing a new, more user-friendly suite of tools for traditional DSP designers. Thus, the company is dropping the term reconfigurability for the new architecture and going with a more traditional name, the streaming data processor (SDP).
Though the SDP will include a reconfigurable processing fabric, it will be substantially altered, the company says. Unlike the older RCP, the new chip won't have the ARM RISC core, and it will support a much higher clock rate. Additionally, it will be implemented in a 0.13-µm CMOS process to meet the signal processing needs of a much broader market.
RECONFIGURABLE COMPUTING:
History:
Although originally proposed in the late 1960s by a researcher at UCLA, reconfigurable computing is a relatively new field of study.
Present developments:
The decades-long delay had mostly to do with a lack of acceptable reconfigurable hardware. Reprogrammable logic chips like field programmable gate arrays (FPGAs) have been around for many years, but these chips have only recently reached gate densities making them suitable for high-end applications. (The densest of the current FPGAs have approximately 100,000 reprogrammable logic gates.) With an anticipated doubling of gate densities every 18 months, the situation will only become more favorable from this point forward.
Explanation:
Reconfigurable computing goes a step beyond programmable chips in the matter of flexibility. It is not only possible but relatively commonplace to "rewrite" the silicon so that it can perform new functions in a split second.
When we talk about reconfigurable computing we’re usually talking about FPGA-based system designs. Unfortunately, that doesn’t qualify the term precisely enough. System designers use FPGAs in many different ways. The most common use of an FPGA is for prototyping the design of an ASIC. In this scenario, the FPGA is present only on the prototype hardware and is replaced by the corresponding ASIC in the final production system. This use of FPGAs has nothing to do with reconfigurable computing.
However, many system designers are choosing to leave the FPGAs as part of the production hardware.
The logic within the FPGA can be changed if or when it is necessary, which has many advantages. For example, hardware bug fixes and upgrades can be administered as easily as their software counterparts. In order to support a new version of a network protocol, you can redesign the internal logic of the FPGA and send the enhancement to the affected customers by email. Once they’ve downloaded the new logic design to the system and restarted it, they’ll be able to use the new version of the protocol. This is configurable computing; reconfigurable computing goes one step further.
Reconfigurable computing involves manipulation of the logic within the FPGA at run-time. In other words, the design of the hardware may change in response to the demands placed upon the system while it is running. Here, the FPGA acts as an execution engine for a variety of different hardware functions — some executing in parallel, others in serial — much as a CPU acts as an execution engine for a variety of software threads. We might even go so far as to call the FPGA a reconfigurable processing unit (RPU).
Reconfigurable computing allows system designers to execute more hardware than they have gates to fit, which works especially well when there are parts of the hardware that are occasionally idle. One theoretical application is a smart cellular phone that supports multiple communication and data protocols, though just one a time. When the phone passes from a geographic region that is served by one protocol into a region that is served by another, the hardware is automatically reconfigured. This is reconfigurable computing at its best, and using this approach it is possible to design systems that do more, cost less, and have shorter design and implementation cycles.
Advantages:
Reconfigurable computing has several advantages.
First, it is possible to achieve greater functionality with a simpler hardware design. Because not all of the logic must be present in the FPGA at all times, the cost of supporting additional features is reduced to the cost of the memory required to store the logic design. Consider again the multiprotocol cellular phone. It would be possible to support as many protocols as could be fit into the available on-board ROM. It is even conceivable that new protocols could be uploaded from a base station to the handheld phone on an as-needed basis, thus requiring no additional memory.
The second advantage is lower system cost, which does not manifest itself exactly as you might expect. On a low-volume product, there will be some production cost savings, which result from the elimination of the expense of ASIC design and fabrication. However, for higher-volume products, the production cost of fixed hardware may actually be lower. We have to think in terms of lifetime system costs to see the savings. Systems based on reconfigurable computing are upgradable in the field. Such changes extend the useful life of the system, thus reducing lifetime costs.
The final advantage of reconfigurable computing is reduced time-to-market. The fact that you’re no longer using an ASIC is a big help in this respect. There are no chip design and prototyping cycles, which eliminates a large amount of development effort. In addition, the logic design remains flexible right up until (and even after) the product ships. This allows an incremental design flow, a luxury not typically available to hardware designers. You can even ship a product that meets the minimum requirements and add features after deployment. In the case of a networked product like a set-top box or cellular telephone, it may even be possible to make such enhancements without customer involvement.
RECONFIGURABLE PROCESSOR
A reconfigurable processor is a microprocessor with erasable hardware that can rewire itself dynamically. This allows the chip to adapt effectively to the programming tasks demanded by the particular software they are interfacing with at any given time. Ideally, the reconfigurable processor can transform itself from a video chip to a central processing unit (cpu) to a graphics chip, for example, all optimized to allow applications to run at the highest possible speed. The new chips can be called a "chip on demand." In practical terms, this ability can translate to immense flexibility in terms of device functions. For example, a single device could serve as both a camera and a tape recorder (among numerous other possibilities): you would simply download the desired software and the processor would reconfigure itself to optimize performance for that function.
We are developing an architecture and a prototype component that will combine a processor and a high performance reconfigurable array on a single chip. The reconfigurable array extends the usefulness and efficiency of the processor by providing the means to tailor its circuits for special tasks. The processor improves the efficiency of the reconfigurable array for irregular, general-purpose computation.
We anticipate that a processor combined with reconfigurable resources can achieve a significant performance improvement over either a separate processor or a separate reconfigurable device on an interesting range of problems drawn from embedded computing applications. As such, we hope to demonstrate that this composite device is an ideal system element for embedded processing.
Reconfigurable devices have proven extremely efficient for certain types of processing tasks. The key to their cost/performance advantage is that conventional processors are often limited by instruction bandwidth and execution restrictions or by an insufficient number or type of functional units. Reconfigurable logic exploits more program parallelism. By dedicating significantly less instruction memory per active computing element, reconfigurable devices achieve a 10x improvement in functional density over microprocessors. At the same time this lower memory ratio allows reconfigurable devices to deploy active capacity at a finer grained level, allowing them to realize a higher yield of their raw capacity, sometimes as much as 10x, than conventional processors.
The high functional density characteristic of reconfigurable devices comes at the expense of the high functional diversity characteristic of microprocessors. Microprocessors have evolved to a highly optimized configuration with clear cost/performance advantages over reconfigurable arrays for a large set of tasks with high functional diversity. By combining a reconfigurable array with a processing core we hope to achieve the best of both worlds.
While it is possible to combine a conventional processor with commercial reconfigurable devices at the circuit board level, integration radically changes the i/o costs and design point for both devices, resulting in a qualitatively different system. Notably, the lower on-chip communication costs allow efficient cooperation between the processor and array at a finer grain than is sensible with discrete designs.
RECONFIGURABLE CHIPS
Reconfigurable chips are simply the extreme end of programmability.
RECONFIGURABLE HARDWARE
Description:
For these reasons, chip designers are turning increasingly to reconfigurable hardware—integrated circuits where the architecture of the internal logic elements can be arranged and rearranged on the fly to fit particular applications.
In order to benefit from run-time reconfiguration, it is necessary that the FPGAs involved have some or all of the following features. The more of these features they have, the more flexible can be the system design. Deciding which hardware objects to execute and when Swapping hardware objects into and out of the reconfigurable logic Performing routing between hardware objects or between hardware objects and the hardware object framework. Of course, having software manage the reconfigurable hardware usually means having an embedded processor or microcontroller on-board. (We expect several vendors to introduce single-chip solutions that combine a CPU core and a block of reconfigurable logic by year’s end.) The embedded software that runs there is called the run-time environment and is analogous to the operating system that manages the execution of multiple software threads. Like threads, hardware objects may have priorities, deadlines, and contexts, etc. It is the job of the run-time environment to organize this information and make decisions based upon it.
The reason we need a run-time environment at all is that there are decisions to be made while the system is running. And as human designers, we are not available to make these decisions. So we impart these responsibilities to a piece of software. This allows us to write our application software at a very high level of abstraction.
Process:
To do this, the run-time environment must first locate space within the RPU that is large enough to execute the given hardware object. It must then perform the necessary routing between the hardware object’s inputs and outputs and the blocks of memory reserved for each data stream. Next, it must stop the appropriate clock, reprogram the internal logic, and restart the RPU. Once the object starts to execute, the run-time environment must continuously monitor the hardware object’s status flags to determine when it is done executing. Once it is done, the caller can be notified and given the results. The run-time environment is then free to reclaim the reconfigurable logic gates that were taken up by that hardware object and to wait for additional requests to arrive from the application software.
Benefits:
The principal benefits of reconfigurable computing are the ability to execute larger hardware designs with fewer gates and to realize the flexibility of a software-based solution while retaining the execution speed of a more traditional, hardware-based approach. This makes doing more with less a reality. In our own business we have seen tremendous cost savings, simply because our systems do not become obsolete as quickly as our competitors because reconfigurable computing enables the addition of new features in the field, allows rapid implementation of new standards and protocols on an as-needed basis, and protects their investment in computing hardware.
Whether you do it for your customers or for yourselves, you should at least consider using reconfigurable computing in your next design. You may find, as we have, that the benefits far exceed the initial learning curve. And as reconfigurable computing becomes more popular, these benefits will only increase.
ADVANTAGES OF RECONFIGURABILITY
Many system-on-a-chip (SoC) computer designs provide reconfigurability options that provide the high performance of hardware with the flexibility of software. To most designers, SoC means encapsulating one or more processing elements—that is, general-purpose embedded processors and/or digital signal processor (DSP) cores—along with memory, input/output devices, and other hardware into a single chip. These versatile chips can perform many different functions. However, while SoCs offer choices, the user can choose only among functions that already reside inside the device. Developers also create ASICs—chips that handle a limited set of tasks but do them very quickly.
The limitation of most types of complex hardware devices—SoCs, ASICs, and general-purpose cpus—is that the logical hardware functions cannot be modified once the silicon design is complete and fabricated. Consequently, developers are typically forced to amortize the cost of SoCs and ASICs over a product lifetime that may be extremely short in today's volatile technology environment.
Solutions involving combinations of cpus and FPGAs allow hardware functionality to be reprogrammed, even in deployed systems, and enable medical instrument OEMs to develop new platforms for applications that require rapid adaptation to input. The technologies combined provide the best of both worlds for system-level design. Careful analysis of computational requirements reveals that many algorithms are well suited to high-speed sequential processing, many can benefit from parallel processing capabilities, and many can be broken down into components that are split between the two. With this in mind, it makes sense to always use the best technology for the job at hand.
CURRENTLY AVAILABLE PROCESSORS
Reconfigurable processors are currently available from Chameleon Systems, Billions of Operations (BOPS), and PACT (Parallel Array Computing Technology).
Among those only Chameleon is providing a design environment, which allows customers to convert their algorithms to hardware configuration by themselves
