26-10-2010, 06:35 PM
A 1-V 36 uW low noise adaptive interface IC for portable biomedical applications
Presented by,
AKHIL MATHEW
S7,Applied Electronics
College Of Engineering, Trivandrum
2007-11 batch
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Contents
Introduction to biopotential amplifiers.
Requirements of a better biopotential amplifiers.
Block diagrams and functional blocks.
Measurement results.
Conclusion.
References.
Introduction
Amplifiers are an important part of modern instrumentation systems for measuring biopotentials. Such measurements involve voltages that often are at low levels, have high source impedances, or both. Amplifiers are required to increase signal strength while maintaining high fidelity. Amplifiers that have been designed specifically for this type of processing of biopotentials are known as biopotential amplifiers
Requirements of a better biopotential amplifier
Signals are difficult to acquire.
The signal amplitudes are very small,which require large amplification,which in turn increases the amount of noise.
They are very prone to noise.
1.In part due to large amplification.
2.In part due their small original amplitude(and hence masked byexternal.stronger signals)
3.In part due to the presence of so many other biological signals in their vicinity,one often sees EMG noise on ECH,EOG noise on EEG,etc
Requirements of a better biopotential amplifier
They are non-stationary: their frequency content changes with time,Fourier based techniques are often not adequate.
The noise spectrum often coincides with that of the signal spectrum, and hence standard filtering approaches fail, need more advances adaptive filtering techniques.
Block diagram of the fully differential adaptive interface.
Three basic functional blocks
Front end instrumentation amplifier.
An analog signal conditioning block including a bandpass filter and a programmable gain amplifier.
A successive approximation register type ADC.
DC coupled fully differential amplifier.
BPF and AGC with configurable bandwidth and gain.
Fully differential SAR ADC.
Chip microphotograph of the interface ASIC
Measurement results
The interface IC was fabricated in a 0.18-μm CMOS technology.
The core area of the interface is 3.2mm×2.8mm, and most of silicon area is consumed by capacitors.
The analog front-end including IA, BPF and PGA consumes 21 μW from a single 1-V supply
Measurement results
The gain is configurable from 31 dB to 52 dB
The bandwidth is configurable from 500 Hz to 4.3 kHz, which covers the spectrum of most biomedical signals
The ADC operates up to 18 kS/s and consumes 15 μWfrom 1-V supply
Measured frequency response of the signal conditioning front end.
Conclusion
The input referred noise density was 95 nV/√Hz and more than 100 dB CMRR was achieved.
The resolution requirement of the ADC has been relaxed with the adaptive full-scale range. The ADC exhibited less than ±1-LSB DNL and ±1.3-LSB INL.
The whole interface consumed only 36 μW from a low supply voltage of 1 V, making it suitable for voltage and power constrained applications.
The design employed fully-differential architecture in the entire analog signal processing path.
References.
[1] R. F. Yazicioglu, P. Merken, R. Puers, and C. V. Hoof, “A 60μW
60nV/√Hz readout front-end for portable biopotential acquisition systems,”
in 2006 IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech.
Papers, San Francisco, CA, Feb. 5–9, 2006, pp. 56–57.
[2] K. A. Ng and P. K. Chan, “A CMOS analog front-end IC for portable
EEG/ECG monitoring applications,” IEEE Trans. Circuits Syst.—I: Regular
Papers, vol. 52, no. 11, pp. 2335–2347, Nov. 2005.
[3] R. F. Yazicioglu, P. Merken, R. Puers, and C. V. Hoof, “Low-power
low-noise 8-channel EEG front-end ASIC for ambulatory acquisition
systems,” in 2006 European Solid-State Circuits Conf. (ESSCIRC), Montreux,Switzerland, Sep. 18–22, 2006, pp. 247–250.
