Ovonic unified memory full report
#6
[attachment=5334]
This article is presented by:
PAWAN KUMAR
PRIMARY AND SECONDARY STORAGE DEVICES




ABSTRACT
A method of automatically configuring a computer peripheral device as a primary device or as a secondary device. There are four possible cases:
(1) no other device present,
(2) legacy primary device present,
(3) legacy secondary device present and
(4) second unconfigured jumperless device present. In each example embodiment, the host computer determines whether any legacy devices are present by sending commands that are ignored by unconfigured jumperless devices.

If a legacy device is present, the host computer sends a command recognized only by an unconfigured jumperless device commanding the particular configuration for the jumperless device. In a first example embodiment, jumperless devices assert a signal after reset with a timing that is dependent on an electronically readable identification on the device. For case (4), the first device to assert the signal becomes the secondary device. For case (4) in the second example embodiment, each jumperless device drives or monitors a line during sequential time periods corresponding to bits in the electronically readable identification number. For case (4) in the third example embodiment, the jumperless devices arbitrate for primary/secondary status without involvement by the host computer by a process that is dependent on the electronically readable identification number on each device.

INTRODUCTION
A method for managing a secondary storage device connected to a computer system having a primary storage device includes hooking a partition session selector device driver in a layered drive structure. An application programming interface call to obtain information related to storage devices connected to the computer system is then performed. The application programming interface call is trapped and the partition session selector device driver is communicated with directly via an interface call to manage a user accessible representation of the primary and secondary storage devices. The interface call communicating with the partition session selector device driver may obtain information related to the secondary storage device, and the method may further include the operation of obtaining information related to storage devices connected to the computer system from a system registry to compile a complete set of data relating to the physical and logical representations of the primary and secondary storage devices. A computer readable media for managing a secondary storage device connected to a computer system having a primary storage device also is described.
Primary storage
Primary storage (or main memory or internal memory), often referred to simply as memory, is the only one directly accessible to the CPU. The CPU continuously reads instructions stored there and executes them as required. Any data actively operated on is also stored there in uniform manner.
Historically, early computers used delay lines, Williams tubes, or rotating magnetic drums as primary storage. By 1954, those unreliable methods were mostly replaced by magnetic core memory, which was still rather cumbersome. Undoubtedly, a revolution was started with the invention of a transistor, that soon enabled then-unbelievable miniaturization of electronic memory via solid-state silicon chip technology.
This led to a modern random-access memory (RAM). It is small-sized, light, but quite expensive at the same time. (The particular types of RAM used for primary storage are also volatile, i.e. they lose the information when not powered).
As shown in the diagram, traditionally there are two more sub-layers of the primary storage, besides main large-capacity RAM:
• Processor registers are located inside the processor. Each register typically holds a word of data (often 32 or 64 bits). CPU instructions instruct the arithmetic and logic unit to perform various calculations or other operations on this data (or with the help of it). Registers are technically among the fastest of all forms of computer data storage.
• Processor cache is an intermediate stage between ultra-fast registers and much slower main memory. It's introduced solely to increase performance of the computer. Most actively used information in the main memory is just duplicated in the cache memory, which is faster, but of much lesser capacity. On the other hand it is much slower, but much larger than processor registers. Multi-level hierarchical cache setup is also commonly used—primary cache being smallest, fastest and located inside the processor; secondary cache being somewhat larger and slower.
Main memory is directly or indirectly connected to the CPU via a memory bus. It is actually two buses (not on the diagram): an address bus and a data bus. The CPU firstly sends a number through an address bus, a number called memory address, that indicates the desired location of data. Then it reads or writes the data itself using the data bus. Additionally, a memory management unit (MMU) is a small device between CPU and RAM recalculating the actual memory address, for example to provide an abstraction of virtual memory or other tasks.
As the RAM types used for primary storage are volatile (cleared at start up), a computer containing only such storage would not have a source to read instructions from, in order to start the computer. Hence, non-volatile primary storage containing a small startup program (BIOS) is used to bootstrap the computer, that is, to read a larger program from non-volatile secondary storage to RAM and start to execute it. A non-volatile technology used for this purpose is called ROM, for read-only memory (the terminology may be somewhat confusing as most ROM types are also capable of random access).
Many types of "ROM" are not literally read only, as updates are possible; however it is slow and memory must be erased in large portions before it can be re-written. Some embedded systems run programs directly from ROM (or similar), because such programs are rarely changed. Standard computers do not store non-rudimentary programs in ROM, rather use large capacities of secondary storage, which is non-volatile as well, and not as costly.
Recently, primary storage and secondary storage in some uses refer to what was historically called, respectively, secondary storage and tertiary storage.
Reply

Important Note..!

If you are not satisfied with above reply ,..Please

ASK HERE

So that we will collect data for you and will made reply to the request....OR try below "QUICK REPLY" box to add a reply to this page
Popular Searches: ovionic unified memory abstract, seminar on ovonic unified memory, n64 roms compatible, ovonic unified memory report, ieee ovonic unified memory, unified library application, cost of ovonic unified memory,

[-]
Quick Reply
Message
Type your reply to this message here.

Image Verification
Please enter the text contained within the image into the text box below it. This process is used to prevent automated spam bots.
Image Verification
(case insensitive)

Messages In This Thread
RE: Ovonic unified memory full report - by Nirja - 28-07-2010, 10:24 AM
RE: Ovonic unified memory full report - by projectsofme - 07-10-2010, 04:29 PM

Possibly Related Threads...
Thread Author Replies Views Last Post
  Transparent electronics full report seminar surveyer 8 25,297 04-04-2018, 07:54 AM
Last Post: Kalyani Wadkar
  wireless charging through microwaves full report project report tiger 90 72,496 27-09-2016, 04:16 AM
Last Post: The icon
  Wireless Power Transmission via Solar Power Satellite full report project topics 32 51,253 30-03-2016, 03:27 PM
Last Post: dhanabhagya
  surge current protection using superconductors full report computer science technology 13 27,542 16-03-2016, 12:03 AM
Last Post: computer science crazy
  paper battery full report project report tiger 57 62,935 16-02-2016, 11:42 AM
Last Post: Guest
  IMOD-Interferometric modulator full report seminar presentation 3 11,779 18-07-2015, 10:14 AM
Last Post: [email protected]
  digital jewellery full report project report tiger 36 67,590 27-04-2015, 01:29 PM
Last Post: seminar report asees
  LOW POWER VLSI On CMOS full report project report tiger 15 22,739 09-12-2014, 06:31 PM
Last Post: seminar report asees
  eddy current brake full report project report tiger 24 34,157 14-09-2014, 08:27 AM
Last Post: Guest
  dense wavelength division multiplexing full report project reporter 3 4,591 16-06-2014, 07:00 PM
Last Post: seminar report asees

Forum Jump: