08-02-2017, 01:47 PM
Hi am jeevan kumar i would like to get details of Dual Use of Power Lines for Design-for-Testability—A CMOS Receiver Design by searching on internet luckily we found this website.... and now i am living at vijayawada and i am studying in the SRKIT and now am doing BTECH final year ECE .....i need full details of this project and ppt also....please help me..please
my mail id is gjeevan234[at]gmail.com please send me...please......