Xiilliinx IISE Siimullattor wiitth Veriillog Testt Fiixtture Tuttoriial

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Overview
This tutorial provides instruction for using the basic features of the Xilinx ISE simulator with the
WebPACK environment. This tutorial uses Verilog test fixture to simulate an example logic
circuit.
More detailed tutorials for the Xilinx ISE tools can be found at

Getting Started
You first need to install Xilinx ISE WebPACK on your PC or laptop. The latest version of the
software is currently 11.1, which is what we use in this tutorial. It is available as a free
download from xilinx.com.
This tutorial uses the project example1-Verilog, from another Digilent tutorial on the Xilinx ISE
WebPACK tools. This project is available as a free download from


Starting Sample Project
First, open Project Navigator by selecting Start> Programs > Xilinx ISE Design Suite 11 ISE
Project Navigator. Once the application opens, specify an ISE project file by selecting File
Open Project and navigate to the appropriate directory to choose your project. In this tutorial,
we use example1-Verilog.xise
Once the project is open, add a Verilog Test Fixture source file to your project. In this source
file, you are able to define circuit inputs over time so the simulator knows how to drive the
outputs.



Verilog Test Fixture
Open the Verilog test fixture in the HDL editor by double-clicking it in the Sources window. If
you examine the contents of the new source file you will see that, like a standard VHDL source
file, the Xilinx tools automatically generate lines of code in the file to get you started with circuit
input definition. This generated code includes:
• a Comment block template for documentation
• a Module statement
• a UUT instantiation
• input initialization
Scroll down to the end of the test fixture file to see the “initial begin” and “end” statements of
the module.