WAIT STATEMENT
#1

Presented by:
Ekta Tiwari

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WAIT STATEMENT
Wait statement

• The WAIT statement gives the designer the ability to suspend the sequential execution of a process or subprogram.
• when a process has a sensitivity list, it always suspends after executing the last sequential statement in the process.
• The wait statement provides an alternate way to suspend the execution of a process.
• Three types of wait statement
• WAIT ON signal changes
• WAIT UNTIL an expression is true
• WAIT FOR a specific amount of time
• WAIT ON signal changes
• SYNTAX:
wait on sensitivity-list;
• wait on A, B, C;
WAIT ON Signal
• process -- No sensitivity list.
• variable TEMP1 ,TEMP2: BIT;
• begin
• TEMP1 :=A and B:
• TEMP2 := C and D;
• TEMP1 := TEMP1 or TEMP2;
• Z<= not TEMP1;
• wait on A, B, C, D; -- Replaces the sensitivity list.
• end process;
WAIT UNTIL an expression is true
• SYNTAX:
wait until boolean-expression ;
• wait until (A = B);
• WAIT UNTIL an expression is true
• PROCESS
• BEGIN
• WAIT UNTIL clock = ‘1’ AND clock’EVENT;
• IF (reset = ‘1’) THEN
• q <= ‘0’;
• ELSE
• q <= d;
• END IF;
• END PROCESS;
WAIT UNTIL
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity cc is
Port ( q : out STD_LOGIC;
d : in STD_LOGIC;
clk : in STD_LOGIC);
end cc;
architecture Behavioral of cc is
begin
PROCESS
BEGIN
wait until clk='1' and clk'event ;
q <= d;
END PROCESS;
end Behavioral;
WAIT FOR a specific amount of time
• SYNTAX:
wait for time-expression ;
• wait for 10ns;
• Using process and wait statements generate a 1 MHz clock that is high for 600ns and low for 400ns
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity clk is
end clk;
Architecture TEST2 of CLK is
Signal Clock: BIT;
begin
process
Begin
Clock <= '1';
Wait for 600 ns;
Clock <= '0';
Wait for 400 ns;
End process ;
End TEST2;
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