VLSI Scaling for Architects

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The Buzz is VLSI Wires are Bad

A lot of talk about VLSI wires
being a problem:
– Delay
– Noise coupling
• What are the characteristics of
chip wires?
– How do they compare to
scaled gates?
• And what does it really mean?
– To CAD developers
– To architects


Predicting the Future
• Is very difficult
– The only guarantee is:
The future will happen, and you will be wrong
• Two approaches
– Think about limitations
• SIA 1994 Roadmap
– Limited oxide thickness, small clock frequency growth, etc.
– Industry hit points above the curve
– Project from current trends
• SIA 1997 Roadmap
– Allow miracles to occur, continue trends
– Project clock rates higher than physically possible
• So use a range of technology scalings
– Better chance of covering the correct answer



Device Scaling Limits
• Limitations to device scaling has been around since I started
– I started working in 3m nMOS, 22 years ago (actually bipolar)
• Worries were
– Short channel effect
– Punchthrough
• drain control of current rather than gate
– Hot electrons
– Parasitic resistances
• Now worries are a little different
– Oxide tunnel currents
– Punchthrough
– Parameter control
– Parasitic resistances