I need to implement the FIR filter with truncated multiplier so please send me the code in verilog

vhdl verilog code of truncated multiplier

Abstract

The scientific computations require intensive multiplication for signal processing (DSP) applications. Therefore, multipliers play a vital and core role in such algorithm used in computations. In digital signal processing, general purpose signal processing (GPSP) and application specific architecture for DSP the computational complexity of algorithms has increased to such extent that they require fast and efficient parallel
multipliers In particular, if the processing has to be performed under real time conditions, such algorithms have to deal with high throughput rates. In many cases implementation of DSP algorithm demands using Application Specific Integrated Circuits (ASICs). This is especially required for image processing applications such as JPEG and MPEG etc. Since development costs for ASICs are high, algorithms should be verified and optized before implementation.


Introduction

However, with recent advancements in very large scale integration (VLSI) technology, hardware implementation has become a desirable alternative. Significant speedup in computation time can be achieved by assigning computation intensive tasks to hardware and by exploiting
the parallelism in algorithms. To date, field programmable gate arrays (FPGAs) have emerged as a platform of choice for efficient hardware implementation of computation intensive algorithms. FPGAs enable a high degree of parallelism and can achieve orders of magnitude speedup over general purpose processors (GPPs). This is a result of increasing embedded resources available on FPGA. FPGA have the benefit of hardware speed and the flexibility of software. The three main factors that play an important role in FPGA based design are the targeted FPGA architecture, electronic design automation (EDA) tools and design techniques employed at the algorithmic level using hardware description languages. In FPGAs, the choice of the optimum multiplier involves three key factors: area, propagation delay and reconfiguration time. Therefore, FPGA has become viable technology and an attractive alternative to ASICs .Multiplication and squaring functions are used extensively in applications such as DSP, image processing and multimedia . A full width digital n×n multiplier computes the 2n output as a weighted sum of partial products . If the product is truncated to n-bits, the leastsignificant columns of the product matrix contribute little to the final result. To take advantage of this, truncated multipliers and squarers do not form all of the leastsignificant columns in the partial-product matrix . As more columns are eliminated, the area and power consumption of the arithmetic unit are significantlyreduced, and in many cases the delay also decreases. The trade-off is that truncating the multiplier matrix introduces additional error into the computation.