30-04-2017, 07:31 AM
Please send me the vhdl code for low power area efficient carry select adder to the mail I'd sherin16189112[at]gmail.com
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vhdl code for low power and area efficient carry select adder
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Please send me the vhdl code for low power area efficient carry select adder to the mail I'd sherin16189112[at]gmail.com
02-05-2017, 09:20 AM
Carry Select Adder (CSLA) is one of the fastest adder used in many data processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is room to reduce the area and the energy consumption in the CSLA. This work uses a simple and efficient transistor level change in the BEC-1 converter to significantly reduce the area and power of the CSLA. Based on this modification, the CSLA 16-b square root architecture (SQRT CSLA) was developed and compared with the CSLA SQRT architecture using an ordinary BEC-1 converter. The proposed design has reduced area and power compared to the CSLA SQRT using ordinary BEC-1 converter with only a slight increase in delay. This work evaluates the performance of the proposed designs in terms of delay, area and power at hand with logical effort and through Cadence Virtuoso. The results analysis shows that the proposed CSLA structure is better than the CSLA SQRT with ordinary BEC-1 converter.
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