30-04-2017, 07:28 AM
Please send me the vhdl code for low power area efficient carry select adder to the mail I'd sherin16189112[at]gmail.com
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vhdl code for low power and area efficient carry select adder
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Please send me the vhdl code for low power area efficient carry select adder to the mail I'd sherin16189112[at]gmail.com
01-05-2017, 03:32 PM
Carry Select Adder (CSLA) is one of the fastest adder used in many data processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is room to reduce the area and the energy consumption in the CSLA. This work uses a simple and efficient gate level modification to significantly reduce the area and power of the CSLA. Based on this modification of 8, 16, 32 and 64-b square root CSLA (SQRT CSLA) architecture have been developed and compared with the CSLA regular SQRT architecture. The proposed design has reduced area and power compared to the regular CSLA SQRT with only a slight increase in delay. This work evaluates the performance of the proposed designs in terms of delay, area, power and their products at hand with logical effort and through custom design and design in 0.18 μm CMOS process technology. The results analysis shows that the proposed CSLA structure is better than the regular CSLA SQRT.
The addition generally affects broadly the overall performance of digital systems and an arithmetic function. In electronic applications, adders are the most used. Applications where they are used are multipliers, DSP to execute diverse algorithms like FFT, FIR and ITR. In microprocessors, millions of instructions are made per second. Therefore, the operating speed is the most important constraint. In digital adders, the rate of addition is limited by the time required to propagate a charge through the adder. The sum for each bit position in an elementary adder is generated sequentially only after the previous bit position has been added and a carry has been propagated to the next position.
The CSLA is used in many computer systems to alleviate the carry propagation delay problem by independently generating multiple carry and then selecting a carry to generate the sum. However, the CSLA is not efficient in the area because it uses multiple pairs of Ripper Carry Adders (RCA) to generate the partial sum and take them by considering the transport input Cin = 0 and Cin = 1, then the final sum and the carry Are selected by the Mux multiplexers). The current CSLA modified SQRT is to use Binary to Excess-1 (BEC) in place of RCA with Cin = 1 in the regular CSLA to achieve lower area and power consumption with a slight increase in delay. The basic idea of the proposed architecture is the one that replaces the BEC by the method of formulation of the modified logic. In this work, we propose an area efficiency transport selection adder sharing the modified logical term. After boolean simplification, you can remove duplicate duplicate cells in the conventional transport selection adder. The multiplexer is used to select the correct output according to its previous execution signal.
The addition generally affects broadly the overall performance of digital systems and an arithmetic function. In electronic applications, adders are the most used. Applications where they are used are multipliers, DSP to execute diverse algorithms like FFT, FIR and ITR. In microprocessors, millions of instructions are made per second. Therefore, the operating speed is the most important constraint. In digital adders, the rate of addition is limited by the time required to propagate a charge through the adder. The sum for each bit position in an elementary adder is generated sequentially only after the previous bit position has been added and a carry has been propagated to the next position.
The CSLA is used in many computer systems to alleviate the carry propagation delay problem by independently generating multiple carry and then selecting a carry to generate the sum. However, the CSLA is not efficient in the area because it uses multiple pairs of Ripper Carry Adders (RCA) to generate the partial sum and take them by considering the transport input Cin = 0 and Cin = 1, then the final sum and the carry Are selected by the Mux multiplexers). The current CSLA modified SQRT is to use Binary to Excess-1 (BEC) in place of RCA with Cin = 1 in the regular CSLA to achieve lower area and power consumption with a slight increase in delay. The basic idea of the proposed architecture is the one that replaces the BEC by the method of formulation of the modified logic. In this work, we propose an area efficiency transport selection adder sharing the modified logical term. After boolean simplification, you can remove duplicate duplicate cells in the conventional transport selection adder. The multiplexer is used to select the correct output according to its previous execution signal.
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