31-03-2016, 03:26 PM
how to write the vhdl code for delaying the clock by 90 degree and test bench
Posts: 6,843
Threads: 4
Joined: Mar 2015
VHDL Code for delaying the clock by 90 degree using Libero IDE and model sim
NET "clk_dac" TNM_NET = "TNM_clk_dac";
TIMESPEC TS_clk_dac = PERIOD "TNM_clk_dac" 27 MHz HIGH 50%; #27MHz
# DAC SLOW
NET "dac_slow_sync_pin1" TNM = "dac_slow_sync";
NET "dac_slow_sync_pin2" TNM = "dac_slow_sync";
NET "dac_slow_sync_pin3" TNM = "dac_slow_sync";
NET "dac_slow_sync_pin4" TNM = "dac_slow_sync";
NET "dac_slow_data_pin1" TNM = "dac_slow_data";
NET "dac_slow_data_pin2" TNM = "dac_slow_data";
NET "dac_slow_data_pin3" TNM = "dac_slow_data";
NET "dac_slow_data_pin4" TNM = "dac_slow_data";
OFFSET = OUT AFTER "clk_dac" REFERENCE_PIN "dac_slow_clk" RISING;
OFFSET = OUT AFTER "clk_dac" REFERENCE_PIN "dac_slow_clk" FALLING;
TIMEGRP "dac_slow_sync" OFFSET = OUT 24 ns AFTER "clk_dac" REFERENCE_PIN "dac_slow_clk" FALLING;
TIMEGRP "dac_slow_data" OFFSET = OUT 35 ns AFTER "clk_dac" REFERENCE_PIN "dac_slow_clk" RISING;