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13-08-2017, 08:30 PM

hi I am Gayatri
I would like to gets details on vhdl code for column bypassing multiplier 12 bits ..
after searching on sites I came to know that I would get it here.
please help me with it.....

jaseela123d · 16-08-2017, 12:20 PM

Multiplication is one of the essential operations in Digital Signal Processing (DSP) applications such as Fast Fourier Transform (FFT), digital filters, etc. The multiplier is designed taking into account the compensations between low power and high speed. The bypass multiplier is an improvement, on the Braun multiplier which is one of the parallel multiplier of the matrix. Commitments, ie, dynamic power and delay of Bypassing multipliers can be reduced using different adders. In this paper we present a comparative study of two - dimensional and two - dimensional derivation multipliers using different adders based on delay, area and power and for 4x4, 8x8 and 16x16 bits in Spartan - 3E FPGA using Xilinx 12.4 ISE and Synopsys respectively.

The low-power design has become a major concern in VLSI design in recent years. There is a great need to investigate techniques to reduce the energy dissipation of devices, such as Digital Signal Processors (DSP). Digital multipliers are essential arithmetic blocks for many DSP applications: filtering, convolution, DCT, Fourier transform, etc. It consumes almost 2/3 of the total power. As a result the optimization of the multipliers for energy is important. In static CMOS, the transition activity dominates the total dissipation of energy due to the charge and discharge of the capacitors. Many previous digital multipliers were aimed at transition or switching reductions to reduce power dissipation as well.

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