Hi am Jayanthi i would like to get details on verilog code for column bypass multiplier. I am living at anantapuramu and i just studying M.TECH . I need to help on verilog code for column bypass multiplier. please send me the code my mail id: passavulajayanthi[at]gmail.com
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Power management has become a major concern in VLSI design in recent years. In this paper we present a low power parallel multiplier design, in which some columns of the multiplier matrix can be turned off each time their outputs are known. In this case, the columns are bridged and, therefore, the switching power is saved. The advantage of this design is that it maintains the original matrix structure without introducing additional boundary cells, as it did in previous designs. Experimental results show that it saves 10% of power for random input. Greater power reduction can be achieved if the operands contain more than 1's. Compared to row multipliers, this approach achieves a greater power reduction with a smaller area overload.
