Hi am Mohamed i would like to get details on verilog code for ternary content addressable memory ..My friend Justin said verilog code for ternary content addressable memory will be available here and now i am living at ......... and i last studied in the college/school ......... and now am doing ....i need help

Verilog CODE-


//-----------------------------------------------------------------------------
//
// Title : decoder2_4
// Design : verilog upload
// Author : Naresh Singh Dobal
// Company : nsd
//
//-----------------------------------------------------------------------------
//
// File : 2 to 4 Decoder using Conditional Operator.v



module decoder2_4 ( din ,dout );

output [3:0] dout ;

input [1:0] din ;

assign dout[3] = din==2'b00 ? 1'b1 : 1'b0;
assign dout[2] = din==2'b01 ? 1'b1 : 1'b0;
assign dout[1] = din==2'b10 ? 1'b1 : 1'b0;
assign dout[0] = din==2'b11 ? 1'b1 : 1'b0;

endmodule