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verilog code for implementation of guessing game

Abstract

Design a clocked synchronous state machine with four inputs,G1-G4,that are connected to pushbuttons. The machine has four outputs L1-L4 connected to Lamps or LED's located near the like-numbered pushbuttons.There is also an ERR output connected to a red lamp. In normal operation the L1-L4 outputs display a 1-out of 4 patterns. At each clock tick pattern is rotated by one position, the clock frequency is about 4MHZ.Guesses are made by pressing a pushbutton, which asserts an input 'G1',when any G1 input is asserted, the ERR output is asserted if the "wrong" pushbutton was pressed, that is, is the G1 input data detected at the clock tick doesnot have the same number as the lamp output that was asserted before the clock tick. Once a guess has been made, play stops and the ERR output maintains the same value for one or more clock ticks until the G1 output is negated, then play resumes.In VHDL system the hardware description language is used to describe the digital systems were it is used in integrated circuits or on printed circuits boards. One of the main advantages of the VHDL is that it allows the system to be modified and verified before the original design is translated into a real one.In general I have explained with the introduction about VHDL programming and state graphs with truth table of the combinational lock machine.
Then the general structure of the VHDL Program and design styles in which includes Behavioural style, structural flow and data flow of this system. In other hand in order to develop this system programming, we are using system software called MODELSIM. It as ability to compilation, stimulation and execution of the waveform